CXL for Memory and More

Intel’s Agilex 7 with R-Tile support works with PCIe 5.0 and CXL.

The co-founder of UnifabriX reviews where CXL fits into the future of memory in the data center.

This year’s Hot Chips event featured a tutorial on the fast-rising CXL standard and its latest iteration—CXL 3.

Astera Labs delivers CXL-attached memory controllers for high-volume deployment.

Compute Express Link is a high-speed interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between host processor and devices such...

The recently announced Universal Chiplet Interconnect Express standard, based on PCIe and CXL, will help simplify chip design.

The capabilities and promise of CXL 2.0 allow us to take data-center architecture and design to a new level.

Compute Express Link is a cache-coherent interconnect for processors, memory expansion, and accelerators that maintains a unified coherent memory space between the CPU and any...

Memory infrastructure gets a boost: OpenCAPI and its OMI subset, along with the CXL, ratchet up performance to address near-memory domain bottlenecks, while Gen-Z focuses on rack...