Actel and HDL Works have jointly optimised HDL Works’ EASE design entry tool for Actel’s Libero Integrated Design Environment (IDE) design flow. The EASE Graphical HDL Design Entry environment provides a ‘fast and accurate’ way of design entry, modification and maintenance of VHDL, Verilog and mixed language designs for FPGAs and ASICs.
EASE gives users the choice of graphical or text-based HDL entry which means the designer can combine their chosen language while improving productivity by through EASE’s facilities: documentation, communication, editing, propagating changes through the design hierarchy and exploring different implementations. EASE automatically generates optimised HDL code in either VHDL or Verilog and supports industry standard version control environments for design and configuration management.
Siemens and other customers have flagged up the importance of an optimised HDL tool flow for the production and maintenance of complex HDL designs. Thomas Rode, design manager for Siemens’ automotive and drives division in Nürnberg, Germany, said, “We’ve used EASE successfully for the implementation of many designs in Actel devices. The main benefit is the enormous reduction in time necessary for editing, debugging and modifying the HDL code”.
The two companies also announced the addition of HDL Works to Actel’s EDA Alliance Programme.