Third-Gen Imaging Radar Processors Built for Level 2+ to 4 ADAS
What you’ll learn:
- How the S32R47 family addresses the requirements of Level 2+ to 4 autonomous driving.
- How higher resolution sensing enables use cases such as detection of vulnerable road users and lost cargo.
- Compatibility with other NXP radar products.
The NXP S32R47 is a radar application microprocessor unit (MPU) that enables next-generation imaging radar sensors to support ADAS Level 2+ to Level 4, addressing the most demanding use cases like debris detection in inclement weather. To serve the fast-growing autonomous-driving market for software-defined vehicles (SDVs), automotive OEMs and tier 1 suppliers need to improve radar performance, as it’s essential for safe, advanced features such as fully automated driving or parking.
The S32R47 imaging radar processor utilizes 16-nm FinFET technology. The third generation of imaging radar processors is said to deliver up to twice the processing power versus the previous generation, alongside improved system cost and power efficiency. In addition, dedicated radar processing accelerators meet demanding sensor-level features for long distance, fine resolution, and extended dynamic range.
According to NXP, in combination with the company’s mmWave radar transceivers, power management, and in-vehicle networking solutions, the S32R47 family meets functional-safety ASIL ISO 26262 ASIL B(D) requirements to prepare the automotive industry for new levels of autonomous driving.
Yole Intelligence’s “Status of the Radar Industry” 2024 report predicts that by 2029, approximately 40% of vehicles entering the road will be passenger cars with driving automation Level 2+(L2+)/ Level 3 (L3). There will also be an increasing number of vehicles with Level 4 (L4).
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Meindert van den Beld, Senior Vice President & General Manager, Radar & ADAS at NXP, said, “The S32R47 can efficiently process three times, or more, antenna channels in real-time than today’s production solutions. It enables improved imaging radar resolution, sensitivity and dynamic range—required by demanding autonomous-driving use cases—while still meeting the stringent power and system cost targets set by OEMs for volume production.”
Denser Point Cloud Output for Next-Gen ADAS
Imaging radar leverages richer point cloud data for more detailed modeling of the environment. This is a key enabler for AI-based perception systems, which allow for assisted and autonomous driving in the most challenging environmental conditions, such as complex urban scenarios.
The S32R47 integrates a high-performance, multicore radar processing system (see figure), allowing denser point cloud output and enhanced algorithms that enable next-generation ADAS systems. This results in better separation of objects, improved detection reliability, and more accurate classification of objects such as vulnerable road users or lost cargo.
The new solution delivers its processing performance in a 38% smaller IC footprint. It also includes AI/ML support for features such as enhanced direction of arrival (DoA) processing (the process of retrieving the direction information of several electromagnetic waves/sources from the outputs of a number of receiving antennas that form a sensor array) and object classification.
The S3243 is a package-compatible variant of the S32R47 to serve different performance classes. The chip is highly software compatible with NXP’s S32R41 and S32R45 radar processors and SAF85xx radar SoCs.
NXP’s new S32R47 radar processing solution is tailored to cover car OEMs’ ever-diversifying use cases and architectures, from corner radar to high-resolution 4D imaging radar. It’s sampling to lead customers. Other automotive applications include:
- Adaptive cruise control
- Autonomous emergency braking
- Highway pilot
- Imaging tadar
- Park assist
- Urban pilot
The S32R43 part is a complementary subset of the S32R47 device family, providing a scalable range of imaging radar chips to address diverse market needs. The S32R platform offers a common architecture for software reuse and fast development, along with a high-performance hardware security engine, OTA update support, and compliance with the newest cybersecurity standards.
