The Crolles2 Alliance has described at the VLSI Symposium in Kyoto, Japan, the creation, under production conditions, of six-transistor SRAM-bit cells with an area less than 0.25 square microns—half the size of earlier solutions—using conventional bulk CMOS technology and 45nm design rules.
Crolles 2 is the research-and-development alliance of Philips, STMicroelectronics and Freescale Semiconductor, and the 1.5Mbit arrays were produced at the Alliance’s 300mm wafer fabrication pilot line in Crolles, France.
The advanced Crolles2 wafer fabrication line is already running pilot production of 90nm CMOS devices on 300mm wafers and is on target to prototype 65nm CMOS during 2005. The new achievements at 45nm are seen as a vital stepping-stone towards future-generation high-volume process technologies.
In general, semiconductor industry customers continuously expect smaller, more highly integrated devices with greater performance and lower power consumption. To meet this demand, semiconductor manufacturers continuously push for smaller geometries, which in itself creates new complexities and manufacturing challenges.
With each new generation of process technology, engineers have typically reduced area by a factor of two. But as process geometries are reduced and oxide layers get thinner, the control of leakage currents becomes a greater challenge. It is a particularly important factor in CMOS devices designed for battery-powered products such as mobile phones and MP3 players.
To meet this challenge, the Crolles2 Alliance is evaluating the extension of conventional CMOS process technology to produce SRAM cells at 45nm while achieving the necessary cell and transistor performance.
Alliance engineers have developed a process that uses existing materials and process flows, maximising the re-use of technology modules. Scientists at Crolles are also evaluating other solutions, including metal-gate technology and the use of high-k dielectric, which are technically more complex and less mature than standard CMOS logic processes.
The Alliance previously demonstrated the feasibility of using conventional architecture to design transistors for 45nm low-cost applications.
The initial strategy was to control gate leakage by limiting the scaling of the gate oxide while other features were scaled down, and to compensate subsequent performance loss by the use of process-induced strained silicon.
Now this principle is being extended to the fabrication of functional sub-0.25-square micron six-transistor SRAM-bit-cells as a practical demonstration of high-density integration. The Alliance used maskless lithography (e-beam) for critical levels to speed-up realisation and to minimise costs in the development phase. The process technology is, however, fully compatible with the optical lithography that will be used in 45-nm CMOS production. These functional 45nm SRAM bit-cells validate the concept of producing very high-density features using low-cost wafers in a conventional process flow.
