Skip navigation
28-nm SRAM Tests Confirm 50% Reduction In Power

28-nm SRAM Tests Confirm 50% Reduction In Power

Early testing of SureCore’s low-power SRAM design revealed more than 50% power savings over other SRAM technologies. The British startup achieved right-first-time silicon at 28 nm and the performance analysis correlated well with simulated data.

SureCore’s patented circuit architecture for energy-efficient memory was born from detailed circuit analysis, architectural improvements, and the use of advanced statistical models. The technology-independent SRAM solution, which can be applied to bulk CMOS, FinFET, and FD-SOI technologies, could double battery life for emerging low-power applications in the mobile, networking, and wearable technology markets.


Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.