Designed for cost-efficient, value-sensitive mobile platforms, the company's family of address-data multiplexed input/output (AD MUX I/O) NOR flash memory employs pin sharing between data and addresses, reducing the number of pins required by the chip. The AD MUX I/O architecture allows either an increase of data-bus width with no pin-count increase or a reduction in pin count without loss of performance. The AD MUX I/O family includes standalone and subsystem solutions, based on 1-bit and 2-bit-per-cell technology, as well as burst-mode and multiple-bank architectures. The devices are available in LFBGA88 (8 mm x 10 mm), LFBGA107 (8 mm x 11 mm), or VFBGA44 (7.5 mm x 5 mm) packages. Standalone memories range from 16- to 64-Mb densities in one-bit-per-cell technology, and from 128- to 256-Mbit densities in two-bit-per-cell technology. The subsystem solutions include 128-Mb NOR flash with 64 Mb of PSRAM and 128-Mb NOR Flash with 32 Mb of PSRAM. Samples are available now with volume production planned for the third quarter. STMICROELECTRONICS, Lexington, MA. (888) 787-3550.
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