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Re-configurable Memory System Shrinks Cost Of SoC Designs

Building upon the first generation of its Self-Test and Repair (STAR) Memory System, the company has developed its new Re-configurable STAR Memory System, which promises to shrink the overal cost of manufacturing system-on-chip (SoC) designs. The system combines non-volatile embedded memory and memory with redundancy to achieve what the company says is an increase in yield regardless of memory type. The memory system consists of a STAR processor, the engine of the system; one or more STAR memories; one or more Area, Speed and Power (ASAP) memories; non-volatile fuses; and programmable memory. The system employs the company’s Fluid Column Redundancy technology, through which defective sections of columns can be disconnected in each bank of memory. This enables the redundant column to quickly repair the defects in a particular section of the memory bank. Furthermore, the company has leveraged its Non-Volatile Electrically Alterable (NOVeA) technology to replace laser programmable fuses in the new memory system. The addition of electrically re-programmable, non-volatile fuses removes the need for external laser repair equipment, thereby lowering the cost of repair. As part of the memory system, the company has also announced its STAR high-density-8M single port embedded SRAM memory for high-bandwidth applications such as communication and networking products. According to the company, the new SRAM can increase data throughput by 20% through efficiencies in the frequency of operation, achieved through the memory’s pipelined architecture. The Re-configurable STAR Memory System will be available in September, 2002 in the 0.18µ and 0.13µ processes at popular foundries with prices starting at $200,000. VIRAGE LOGIC, Fremont, CA. (877) 360-6690.


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TAGS: Digital ICs
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