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Souped-Up Synchronous DRAM Supports High-Speed Processors

A 256-MB double data rate (DDR) synchronous DRAM, the W3E32M72S-XSBX is a high-density memory chip designed to support high-performance processors. Organized as 32 MB by 72, it can run at clock rates of 200, 250 and 266 MHz. The device includes four internal memory banks for concurrent operation. It has bidirectional data strobe (DQS) per byte and differential clock inputs. A data mask is incorporated for masking write data per byte. Both the core supply voltage and I/O supply voltage are 2.5V, ±0.2V. The memory is packaged in a 208-lead plastic ball-grid array (PBGA) that occupies 352 mm2 and measures 16 mm x 22 mm with a maximum body thickness of 3.12 mm. It is suitable for high-reliability applications and is available in commercial, industrial and military temperature grades. Price is $250 each/1,000. WHITE ELECTRONIC DESIGNS CORP., Phoenix, AZ. (602) 437-1520.


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TAGS: Digital ICs
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