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SRAMs Achieve 100% Bus Utilization

By eliminating idle bus turnaround cycles, the ZBT Zero Bus Turnaround (ZBT) Sync Burst, 2-Meg, 3.3V SRAMs provide users with 100% bus utilization. Conventional synchronous-burst SRAMs require idle cycles to turn the bus around when switching reads and writes. These idle cycles increase the time required for each bus transition. The ZBT architecture out-performs that of conventional synchronous-burst SRAMs by eliminating these dead cycles to give systems higher performance and increased bandwidth. All critical timing parameters are referenced to the rising edge of the synchronous clock to further simplify the design of high bandwidth switching systems. The new SRAMs come in JEDEC-standard 100-pin TQFPs in flow-through or pipelined organizations.


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TAGS: Digital ICs
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