Electronic Design

STT Technology Puts A New Spin On MRAM

MRAM’s full potential has been one of the electronics industry’s holy grails—until now. Maybe. Its promise includes nonvolatility, fast read and write times, and unlimited endurance.

Power requirements and density have been limitations in the past, though current MRAM technology has succeeded in a number of niche applications. MRAM is complementary with technologies it may replace, including SRAM, DRAM, and flash memory.

Crocus Technology’s STT-based (Spin Transfer Torque) MRAM technology looks to reduce program write currents while providing high-density chips that can challenge other memory technologies, retaining all of MRAM’s advantages. It targets the latest 65- and 45-nm chip technologies and supersedes the company’s firstgeneration MRAM, which was based on 130-nm thermal assisted switching (TAS) that addressed MRAM stability and reliability issues.

STT’s proprietary cell structure reduces the programming current required at the magnetic tunnel junction (MTJ) to write data by a factor of five (Fig. 1). The latest demonstration chips exhibited a dynamic of 2 × 106 A/cm2 with a 10-ns programming pulse.

The STT implementation adds only three or four steps to the process flow (Fig. 2). This improves integration in embedded microcontroller applications. The additional steps typically incur less than a 5% cost overhead and extend fab cycle time by less than 15%.

Crocus Technology expects an improved version of STT to move the technology into the 45-nm realm and beyond. This will require further stabilization as finer geometries are utilized. Implementations of 1-Mbit planar chips based on 65-nm STT are expected in 2010. The technology has the potential for chips as large as 256 Mbits.


TAGS: Digital ICs
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