1. SiFive's Freedom E310 32-bit microcontroller is the first commercially available RISC-V chip.
A RISC-V chip is now available in the form of SiFive's Freedom E310 (Fig. 1). The Freedom E310 is a microcontroller with a 32-bit RV32IMAC architecture. The RV32IMAC designation is an abbreviation for the standard RISC-V features including 32-bit support (RV32), integer support (I), hardware integer multiplication and division (M), atomic real-time instructions (A), and support for the 32-bit and compact (C) 16-bit instruction set. The chip has 16 32-bit registers and no hardware stack. As with many RISC systems, it uses a jump and link (JAL) instruction to save a return address in a register.
The chip can be found on the HiFive1 Arduino-compatible board (Fig. 2). It is available for $59 at the CrowdSupply project site. The chip is tiny compared to the Future Technology Devices International's (FTDI) USB controller used for programming support.
2. The HiFive1 is an Arduino-compatible board running SiFive's E310 32-bit microcontroller.
The E310 runs at a fast 320 MHz and delivers 1.61 DMIPS/MHz, versus 1.3 for an Intel Curie or 0.93 for Atmel ATSAMD21G18 (Fig. 3). The high clock rate allows the chip to be used in applications requiring more performance while running at a lower speed to deliver very-low-power operation.
3. The E310 can run at 320 MHz but it compares nicely to other 32-bit platforms in terms of performance (DMIPS/MHz) and power utilization (DMIPS/mW).
The peripheral complement of the E310 is on par with the typical 32-bit microcontroller (Fig. 4). It has 16 Kbytes of SRAM and a 16 Kbyte instruction cache. It actually uses a quad SPI (QSPI) flash memory interface that supports execute-in-place operation with a 32-byte burst mode. The HiFive1 board has a 128 Mbit (16 Mbyte) SPI flash chip. This means that the E310 is at least a two-chip solution, but the SPI flash chips are tiny and available in a wide range of capacities.
4. The E310 incorporates the usual functional blocks found in a microcontroller, although there is no on-chip flash memory.
The use of QSPI flash is interesting because the system's large instruction cache provides the performance boost while allowing developers to select the amount of flash memory required by an application. SKUs for many single-chip solutions from vendors are simply enumerations of different capacity flash memory.
The chip has two additional QSPI ports, along with two UARTs. There is a 16-bit and 8-bit PWM. A more detailed block diagram (Fig. 4) highlights additional features like on-chip ROM, one-time-programming (OTP) memory, and power management.
The one thing lacking in the E310 is analog support, but this just puts the chip in the same ballpark as the majority of microcontrollers that only provide digital peripherals. Off-chip analog peripheral chips are available and often utilized where higher accuracy or performance is needed.
The E310 is part of SiFive's Freedom Everyware family and actually addresses a wide range of platforms, including MIPS and ARM. In the microcontroller space, the Cortex-M0 is the low-end darling and; the E310 and RISC-V look to challenge it and other low-power platforms used in Internet of Things (IoT) mobile devices.
The E310 is only one chip so far, but it will have some interesting competition as it moves into the IoT space. Security is an issue, and ARM's new Cortex-M23 and Cortex-M33 architectures incorporate ARM TrustZone support. Chips based on these architectures are a step up from the convention 32-bit microcontrollers, but the E310 does have features like OTP that can help in increasing the security of an IoT device.
I don't expect SiFive to develop a family of chips to take on the microcontroller behemoths. Instead, the E310 is more intended to whet the appetite of developers who are looking for custom chips based on the E310. SiFive estimates that a custom chip can be delivered for about $100,000. This is less that many licensing fees for other commercial processor architectures and includes delivery of production chips. It is one advantage of using third-party foundries.
The E310 is actually an open-source design available to anyone. RISC-V is actually an open instruction set architecture (ISA) where E310 is just one incarnation. It is possible to license the E310 and variations from SiFive, as well. This approach might be of more interest for the higher end Freedom Unleashed platform that includes multicore and virtual memory support for chips capable of running operating systems like Linux.
Novix NC4016 – A Blast from the Past
The E310 reminded me of a number of chips from the past where a new approach was taken and there was a lot of interest in certain sectors. One was the Novix NC4016 (Fig. 6) that also took a RISC approach, although it had a stack orientation for running Charles Moore's Forth code.
6. The Novix NC4016 (left) was a 16-bit, Forth microprocessor from the 1980's. The E310 is a 32-bit RISC-V microprocessor released in 2016.
It was designed back in the 1980's and was 20 times faster at running Forth code than the Motorola 68000. There was also a Small C compiler, although the chip was primarily for applications written in Forth.
The chip was useful in embedded applications and was even licensed by Harris Semiconductor, where it was rebranded as the RTX2000. An 8-MHz radiation-hardened version implemented in CMOS Silicon-On-Sapphire was used in some satellites.
Forth is still around, but Forth chips are not. The competition was stiff, and it included not only the architecture but the software and vendor support.
Why RISC-V Will Succeed
So how is RISC-V going to fare?
It is necessary to start somewhere, and RISC-V ISA is that starting point. With the exception of virtual machine support, the definition and support is pretty much cast in concrete, allowing the next step to occur. That is the architectural implementations. SiFive is the one leading the charge, and its Freedom series is really about silicon IP. The final step is the hardware like the E310, but the E310 is only the start.
What does RISC-V have going for it, then?
First, third-party fabs are the norm these days. All that is needed for making a chip is the IP and cash. Chips come out the other end of the fabs.
Second, vendor and infrastructure support for RISC-V is significant and growing. The RISC-V membership list includes a wide range of notable companies like NVidia, Microsemi, Microsoft, and Google.
Third, the type of support, especially on the software side, is significant. An open-source toolset is available, as well as tools like Rocket for generating silicon IP based on a selection of RISC-V attributes. This is just for the processor core, but it is the starting point for a custom design.
Fourth, RISC-V is rooted in open source. This is not necessarily true for all incarnations, but it is for the E310 and the RISC-V ISA. Rocket essentially delivers open-source designs.
Finally, IoT is pushing design attributes like customization, low power, high performance, and low cost. SiFive and RISC-V address each of these attributes.