Electronic Design
Multicore MIPS Smaller Than Atom

Multicore MIPS Smaller Than Atom

MIPS has announced its latest multicore architecture, the MIPS32 1074K. Three of the cores take up about the same amount of chip real estate as one Intel Atom. The MIPS approach delivers more than double the performance while consuming less power. Still, the Atom is a 64-bit processor while the MIPS32 is a 32-bit architecture so the 1074K is actually more comparable to Arm's latest offering, the Corex-A15 (see Arm Delivers More Multicore Multimedia). All three architectures support virtualization and SMP processing.

The 1074K archtecture is designed to handle a 1.5GHz clock and the latest 40nm technology. It uses a 15-stage pipeline, superscalar, out-of-order high-performance design. A quad core system delivers more than 15000 CoreMarks and 12000 DMIPS. It is binary compatible with the MIPS32 24K and 74K series of processor architectures. The 1074K is expected to be used in a wide range of applications from WiFi routers to multiroom set top boxes (STB).

Major components include the Coherence Management (CM) unit, the I/O Coherence Unit (IOCU), the Cluster Power Controller (CPC) and the Global Interrupt Controller (GIC). The CM provides a high throughput coherence fabric with 256-bit wide buses for key datapaths and for external read and write data interfaces to L2 cache. It also handles L1 cache-to-cache transfers, speculative reads to external memory, and globalized cache operations. The IOCU delivers hardware acceleration for I/O coherence. The CPC handles multicore power gating, clock gating, and reset management. Each core is its own separate power domain. Power and clock gating can significantly reduce power consumption. The GIC can route interrupts to a specific core or virtual processing element (VPE). It can handle up to 256 interrupts.

Each core has its own IEEE 754-compliant Floating Point Unit (FPU) that is compliant with MIPS' 64-bit FPU architecture. It supports single- and double-precision data types. The FPU core uses a separate in-order, dual-issue pipeline decoupled from integer pipeline in each core.

The new architecture incorporates a number of improvements including indirect jump caching. This came out of profiling work done using other MIPS platforms. The caching provides a 20%-30% performance improvement.

The 1074K includes PDtrace(see MIPS On-Chip Debug Hardware) and performance trace support. EJTAG support is also included. The hardware also provides inter-processor cross-triggering debug support. There are independent hardware triggers per core. The "trace funnel" can aggregate tagged trace data from each core to the on-chip trace buffer or an external trace probe. A system can provide self-debug support and remote debug over a network connection.

The 1074K comes with a wide range of third party support. The system can handle popular platforms like SMP Android. The Eclipse-based MIPS Navigator ICS is only one of the development tools available to developers.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.