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New PSoC 6 Sports Dual, Asymmetric 32-bit Cores with Enhanced Security

New PSoC 6 Sports Dual, Asymmetric 32-bit Cores with Enhanced Security

Cypress Semiconductor extends its PSoC family with the dual-core PSoC 6. One core can be used as a security processor.

Cypress Semiconductor’s PSoC was revolutionary when it first came out. It used a proprietary 8-bit core that was surrounded by configurable digital and analog blocks. This allowed a single stock keeping unit (SKU) to deliver an amazing combination of peripherals based upon the application and how the developer decided to configure the system. One design might use a digital block for a timer while another might use it as a custom serial interface. The PSoC family has grown using different cores and now employ ARM Cortex-M cores.

The PSoC 6 is Cypress’ latest offering, revealed at Embedded World 2017, and it’s almost as revolutionary as the original PSoC. It is available in a dual-core configuration with a Cortex-M0+ and a Cortex-M4 (Fig. 1). A single Cortex-M4 core version will also be available. The dual-core system allows one core to operate as a security processor with full control over the other core and peripheral access.

1. The PSoC 6 is available in a dual-core configuration with a Cortex-M4 and Cortex-M0+.

The PSoC 6 story is more about the dual-core solution. It still has the configurable digital and analog blocks, and there are improvements, but the dual-core approach has major implications for security and low-power operation. The 150-MHz Cortex-M4 has single precision floating point support and it is managed by the 100 MHz Cortex-M0+, which is designed to run in secure mode.

There is independent power management and interprocessor communication (IPC) hardware, plus shared SRAM support. The Cortex-M0+ can block the Cortex-M4’s access to blocks of memory and peripheral interfaces. The system can use as little as 200-µA. MCU active power is 22 μA/MHz. Deep sleep mode cuts power consumption down to 4.5 μA.

The Cortex-M0+ manages the Trusted Execution Environments (TEE). These are multiple hardware-based, secure enclaves. The hardware security support also includes secure boot, secure key storage, and a real hardware random number generator that uses the CapSense interface for randomization. Each chip has a unique ID, as well.

The system will support HyperBus and SD card support in future versions, but it already uses QSPI for eXecute-in-place (XIP) support using encrypted or unencrypted, off-chip storage. On-chip flash up to 1 Mbyte will be available. RAM tops out at 288 Kbytes. Each core has an 8 Kbyte cache.

Analog support is significant, with an on-chip buck converter to a 12-bit ADC and DAC. The initial chips will have a pair of op amps and two comparators. The PSoC 6 will have a range of wireless options, starting with Bluetooth Low Energy 5.0 (BLE) and moving into other technologies like Wi-Fi.

The initial PSoC 6 develop kit (Fig. 2) is impressive as well. Of course, it has a PSoC 6 and a PSoC 5 to handle programming. It has a USB Type-C interface that provides a high-speed interface and it also supports a power usage model where external power can be routed through Type-C connector. The Type-C support is actually independent of PSoC 6 and provided by Cypress EZ-PD chips. One advantage the board has over previous platforms is that it can measure the power utilization of just the PSoC 6

Fig. 2
2. The PSoC 6 developer board supports USB Type-C with intelligent power distribution.

The board is compatible with Arduino Uno modules. It has a 512 Mbit QSPI NOR flash chip and an on-board antenna for the Bluetooth support. The Capsense touch support includes a section that can be used for a range of buttons and sliders.

The PSoC 6 supported by a range of software including PSoC Creator. There is also a common peripheral library that allows most of the PSoC features to be utilized without dealing with most customized chip design tools.

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