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Single Cycle 120MHz Cortex-M3 Delivers 150 DMIPS

Single Cycle 120MHz Cortex-M3 Delivers 150 DMIPS

STmicroelectronics' Cortex-M3-based, 90nm STM32 F-2 family (Fig. 1) utilizes a single level, instruction branch cache (Fig. 2) to provide single cycle execution from on-chip flash at 120 MHz. The 256 entry branch cache, called the Adaptive RealTime (ART) memory accelerator, has 128-bit entries that hold eight 16-bit instructions or four 32-bit instructions. The chip also caches the next block of instruction so the system will run at full speed as long as any branches are to instructions contained in the cache. Of course, a cache miss results in a single wait state.

STmicro's STM32 F-2 also has an 8 entry data cache for flash-based data. The on-chip SRAM runs at full bus speeds and does not require a cache. 4 Kbytes of SRAM can be battery backed. The chips are available with up to 1 Mbyte of flash and 128 Kbytes of SRAM. The latter is split into 16 Kbyte and 112 Kbyte blocks allowing simultaneous access to SRAM by two devices. There is also 528 bytes of OTP memory.

The caching system gives the STM F-2 an edge compared to the competition that typically adds wait states or implements a more conventional caching system. In the latter case, the flash memory is often not as wide with designers turning to a larger cache and all executed instructions come through the cache. STmicro's approach tends to have a cache that changes only occasionally even for a large program with many loops and conditionals.

The 32-bit STM F-2 employs a 32-bit AHB bus matrix (Fig. 3). The DMA channels and processor core have multiple connections to peripherals reducing possible access delays. The dedicated processor to flash connection means the processor always runs at full speed.

Peripherals within the family include 10/100 Ethernet, USB OTG, two CAN 2.0B interfaces, an SDIO port, three 30 Mbit/s SPI ports, three I2C ports, and six 7.5 Mbit/s USARTs. Audio support is provided via I2S and USB PLL and data synchronization. The 48 Mbyte/s camera interface handles 8- to 14-bit data. There are two motor control PWMs, 12 general purpose timers, and two 32-bit timers.

Designers can trade off a 60 MHz external static memory interface with LCD support. The crypto engine includes a hardware random number generator and supports 3DES, AES256/SHA-1, MD5, and HMAC. GPIO can run up to 60 MHz. The analog side includes three 12-bit ADCs that handle up to 2 Msamples/s or 6 Msamples/s in interleaved mode. There is also a 12-bit DAC.

The core runs at 1.2V. The 4mm by 4mm WLCSP packaged version can run as low as 1.65V Vdd. The LQFP and BGA packages bottom out at 1.8V. The processor uses 188μA/MHz. There are a number of advanced low-power modes including various battery backup options. The realtime clock (RTC) uses less than 1μA while the 4 Kbytes of SRAM use about the same amount. Combined they use less than 2μA.

The latest chips are supported by a range of third party development tools. The STM3220G-EVAL dev kit (Fig. 4) is priced about $200.

Pricing for the STM32-F2 series starts at $3.18 for the STM32F205RBT6 with 128 Kbytes of flash and 64 Kbytes SRAM in the LQFP64 package.

TAGS: Digital ICs
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