ARM expects its 32-bit Cortex-A12 architecture to show up in chips in 2014. It delivers a 40% performance boost over the Cortex-A9 while using the same amount of power. Also, it provides high-end features like big.LITTLE support (see “Little Core Shares Big Core Architecture”), 40-bit addressing for access to 1 Tbyte of virtual memory, security features for hardware virtualization, and ARM’s TrustZone support.
The Cortex-A12 fits between the Cortex-A7/A9 and Cortex-A15, which is the basis for a number of multicore systems-on-chip (SoCs) including Nvidia’s Tegra 4 (see “Quad Cortex-A15 + 72-Core GeForce GPU = Tegra 4”). It fits well below ARM’s 64-bit Cortex-A50 offerings, though the Cortex-A12 will support up to four cores while targeting the latest 28-nm technology (see the figure).
1. ARM’s 32-bit Cortex-A12 supports up to four cores and can be combined with the Mali-T622 or Mali-V500 GPUs.
- Quad Cortex-A15 + 72-Core GeForce GPU = Tegra 4
- Delivering 64-Bit Arm Platforms
- Little Core Shares Big Core Architecture
The architecture was designed from the ground up. It incorporates a dual-issue, out-of-order (OoO), 11-stage, dynamic length pipeline that’s tightly integrated with the NEON SIMD engine and floating-point units. The L1 and L2 caches have been optimized for mobile workloads. Its CPU and GPU cores are connected via a 128-bit AMBA ACE (AXI Coherency Extensions). The Accelerator Coherency Port (ACP) provides I/O coherency for DMA units.
The chips will include an ARM peripheral port designed for low-latency peripherals that do not have to utilize the AMBA ACE, eliminating related memory traffic congestion.
The architecture supports the midrange Mali-T622 GPU (see “Mobile GPU Architecture Supports Emerging Compression Standard”). This second-generation GPU supports OpenCL 1.1, Renderscript Compute, and OpenCL ES 3.0. The Cortex-A12 also can be paired with the Mali-V500 video engine, which includes up to eight cores. It can handle 1080p 60-Hz HD video encode and decode and is scalable to 4K120. It also supports AFBC (ARM frame buffer compression), which can reduce bandwidth by 50%. It supports a TrustZone secure video path for content protection as well.
The Cortex-A12 comes with Processor Optimization Pack (POP) IP support that was used with the Cortex-A50 family and the Cortex-A7, Cortex-A15, Cortex-A5, and Cortex-A9. For big.LITTLE support, the Cortex-A12 will be paired with a Cortex-A7 core. It provides a lower-cost, lower-power solution to a Cortex-A15/A7 pairing.