Imec And Altos Collaborate On Chip Design And Prototyping

Leuven, Belgium and San Jose, California: Belgian electronics research centre Imec and Altos Design Automation have agreed to establish a library re-characterization service based on Altos characterization tools. With this collaboration, Imec will extend its ASIC prototyping and volume fabrication service with library re-characterization which is essential when designing in 65nm and 40nm nodes.

Imec and Altos will collaborate to offer re-characterization of standard foundry or library vendor libraries including core and IO cells at different process, temperatures and/or voltages. The library re-characterization is based on Altos’ Liberate cell characterization product. Validation of the re-characterization will be performed using Altos’ Liberate LV library validation system.

When designing in 65nm and 40nm nodes, re-characterization of standard cell libraries is becoming increasingly necessary in order to get the delay, timing constraints, switching power, leakage and noise for all the corners needed for accurate design signoff. Standard design libraries offered by foundries or library vendors are characterized for certain conditions but the de-rating factors do not apply to all temperatures and voltages. To guarantee first time right designs, library re-characterization becomes essential for 65nm and 40nm technologies.

“The demands of advanced process nodes are driving the requirement to have cells characterized at more temperatures and voltage levels than ever before;” said Jim McCanny, CEO at Altos. “This is because accurate modelling of instance specific voltage and temperature variations cannot be achieved with only one temperature and voltage choice per process corner.  In addition the prevalent use of low power design methods means that designers can no longer afford to over-design to extreme corner conditions but need to target library corners that are more relevant to their design application.”

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