Changing Requirements for ASIC Design

Sept. 23, 2005
It’s a changing world. In 1851, the headline of an editorial in an Indiana newspaper urged readers to “Go West, Young Man!” Fast forward 150 years, and you might see a headline in Electronic Design imploring a designer to “Go Higher!”...

It’s a changing world. In 1851, the headline of an editorial in an Indiana newspaper urged readers to “Go West, Young Man!” Fast forward 150 years, and you might see a headline in Electronic Design imploring a designer to “Go Higher!”

"Go higher," of course, refers to the movement to higher levels of abstraction in chip design—above the register transfer level (RTL), in fact—or what Dataquest refers to as the electronic system level (ESL). Going higher offers design teams a means to differentiate, manage complexity, and cope with time-to-market pressures. While this move is inevitable, it results in changing requirements for ASIC design.

Many of today's ASICs implement highly complex, intricate mathematical algorithms in a mix of hardware and software. As such, these designs require a comprehensive design process that starts from an initial description of the target application. This description should be detailed enough to model the algorithmic specification, but it needn't be tied to any particular implementation (e.g. logic gates, software executing on an embedded processor). This model should also be tightly coupled to existing implementation flows and used as a functional reference model to verify final implementations.

Such a description will enable designers to make architectural tradeoffs, which have a large impact on the final performance and power consumed by the chip as well as its size. In addition, the ability to add certain implementation details (such as datapath width) to the algorithmic model gives the downstream RTL and software design flows more guidance for their respective implementations. The verification groups now also have a detailed functional model by which to test designs. The net result is a higher-quality implementation in a shorter design time.

Many EDA vendors have talked about such a flow. The beauty of this particular methodology is that it leverages the popularity of an existing design-entry language such as, say, Matlab, a numerical analysis and visualization environment from The MathWorks. In the application areas in which ASIC design activity is highest—wireless communications, imaging and audio processing, for example—design teams are most likely already using Matlab as the foundation for their design process. It’s not uncommon for entire chips to be first described in Matlab. That’s because it is an excellent language for expressing complex mathematical algorithms that are at the core of many new ASICs.

Increasing complexity, ever-changing design requirements, and mathematical breakthroughs are forcing ASIC design teams to compete on the novelty and strength of their algorithms rather than the efficiency of their RTL implementation. As a result, comprehensive algorithm exploration and simulation has become far more important.

With today’s design constraints, the clarion call is not “Go West,” but rather “Go Higher.” And while the changing requirements of ASIC design may seem daunting, tools exist today to ease the transition to ESL.

Niraj Shah can be reached at: [email protected].

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