Termination Array Squeezes Into Chip-Scale Package

Combining 32 resistors in a single chip-scale package, the CSPDDR100 is a termination array for double-data rate (DDR) RAMs or series stub terminated logic (SSTL). Applications for the array are in computer-graphics accelerator cards, and network infrastructure equipment such as servers, routers, and switches.
Built using state-of-the-art thin-film technology, the resistors are said to have excellent high-frequency performance (>3GHz). To provide better impedance matching of the interconnections, and thus improved signal integrity on the transmission line, the resistors are trimmed to an absolute tolerance of ±1% over temperature. It is said that implementing the CSPDDR100 in a high-speed memory system will reduce ringing on the transmission lines, reduce crosstalk between lines, increase noise margins, and minimize EMI/RFI emission problems.
Pricing is $0.41 each/100,000. Samples are available now and production lead time is six to eight weeks ARO.