The Importance of Chip-Scale Packaging in Electronics

Achieving the circuit densities we need for the next generation of electronics demands advanced packaging and chip-scale interconnect solutions.
Nov. 18, 2025

What you'll learn:

  • The need to look for alternative packaging solutions to handle AI chores.
  • How Sarcina Technology's interposers can meet insertion loss and crosstalk requirements.

Artificial-intelligence (AI) workloads and other advanced computing applications continue to expand, pressuring the development community with the dual challenges of performance and manufacturability. Traditional systems-on-chip (SoCs) are approaching their limits in terms of size, yield, and cost, so designers are turning to alternative solutions such as chiplet-based architectures

Sarcina Technology is focused on enabling package design to achieve the system-level performance required for next-generation AI systems. In this podcast, we talk to Larry Zu, CEO at Sarcina Technology, about how the company is deploying interconnect to minimize signal crosstalk and enhance signal integrity. 

Sarcina's novel interposer solutions meet stringent insertion loss and crosstalk requirements, enabling robust, high-bandwidth communication for next-generation AI accelerators and high-performance computing (HPC) systems.

>>Check out this TechXchange for similar content.

Dreamstime.com
Chip Packaging TechXchange
Taking a close look at chip packaging technology including new advances such as chiplets.

About the Author

Alix Paultre

Editor-at-Large, Electronic Design

An Army veteran, Alix Paultre was a signals intelligence soldier on the East/West German border in the early ‘80s, and eventually wound up helping launch and run a publication on consumer electronics for the US military stationed in Europe. Alix first began in this industry in 1998 at Electronic Products magazine, and since then has worked for a variety of publications in the embedded electronic engineering space. Alix currently lives in Wiesbaden, Germany.

Also check out his YouTube watch-collecting channel, Talking Timepieces

Larry Zu

Founder and CEO, Sarcina Technology

Larry Zu has grown Sarcina from designing packages for a few small companies, to doing package designs for top semiconductor companies in the world. From 2014 to 2018, he led the expansion of Sarcina beyond package design into final test and wafer sort hardware and software development.

Larry is semiconductor veteran who started his career at Bell Labs, before moving on to DEC, Intel, and TSMC. Along the way he developed a proven track record of delivering successful products including the Alpha, Itanium 2, Pentium 4, and XBOX 360 microprocessors. Over his career, he has taped out nearly 1,000 packages with a greater than 99% first tape-out success rate.

Larry received his B.S. in Physics from Peking University and his Ph.D. in Electrical & Computer Engineering from Rutgers University. He has many refereed IEEE publications and holds multiple U.S. patents that have been used in leading US companies' key products.

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