DesignCon, held Jan. 31 to Feb. 1 in Santa Clara, provided companies an opportunity to highlight their products and technologies for high-speed digital-communications applications. Relevant products from DesignCon exhibitors including ANSYS, Cadence Design Systems, Keysight Technologies, Molex, National Instruments, Rohde & Schwarz, and Tektronix were highlighted in our January Special Report on high-speed digital design, interconnect, and test.1 In the runup to and during the event, companies have reported additional capabilities related to IP, components, interconnect, and test and measurement.
Leading up to the event, Rambus Inc. announced its GDDR6 (Graphics Double Data Rate) Memory PHY IP Core targeted for high-performance applications including cryptocurrency mining, AI, ADAS, and networking. Leveraging almost 30 years of high-speed interface design expertise and using advanced leading-edge FinFET process nodes, the company reported, the Rambus GDDR6 PHY architecture will provide speeds of up to 16 Gb/s while utilizing established packaging and testing techniques.
“The high bandwidth delivered by GDDR6 makes it uniquely qualified to perform data-intensive applications such as HPC, AI, autonomous vehicles, and high-speed networking,” said Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces Division, in a press release. “We are excited to be the first IP provider to offer a GDDR6 PHY solution with industry-leading performance designed with power efficiency and high signal margins for these applications.”
PCIe compliance solution
Anritsu at DesignCon reported that its MP1900A Signal Quality Analyzer-R (SQA-R) has been certified as a compliance test solution for PCI Express (PCIe) 3.0 technology Link Equalization (Link EQ) tests and Receiver (Rx) Jitter Tolerance tests by the PCI-SIG consortium. With support for the PCI Express 3.0 specification, as well as expandability to PCI Express 4.0 and 5.0 specifications, the MP1900A helps control capital equipment expenses while supporting various tests, such as PHY layer electrical characteristics and protocol tests, using a high-quality waveform pulse pattern generator (PPG) and high-sensitivity error detector (ED), the company reported.
Anritsu describes the MP1900A SQA-R (Figure 1) as a multichannel bit-error-rate tester (BERT) offering high-level, high-waveform-quality PPG with 115-fs intrinsic jitter, high-accuracy jitter generation sources (SJ, RJ, SSC, and BUJ), and a noise source for generating CM-I/DM-I/white noise. The instrument has a 15-mV high-input-sensitivity error detector (ED) with embedded clock recovery, allowing accurate BER tests to be made, even with a very small closed eye.
Courtesy of Anritsu
The certified test solution integrates the MP1900A SQA-R with the Teledyne LeCroy SDA830Zi-B serial data analyzer, which has up to 30 GHz of bandwidth and an 80-GS/s sample rate. Engineers can use the integrated solution to perform calibration for evaluating the PHY layer of PCI Express 3.0 (8 GT/s) technology add-in cards and system boards, as well as Link EQ tests for verification of the device-under-test communications state. Rx tests to measure the DUT stress tolerance can be performed, as well. Using the SQA-R and SDA830Zi-B supports high-repeatability testing, as well as troubleshooting analysis. Inclusion of the Teledyne LeCroy instrument also allows support for transmission-side tests.
Clock recovery and signal integrity
Keysight Technologies demonstrated several new capabilities at DesignCon, including the new N1076B 16/32/64-Gbaud Electrical Clock Recovery Solution for analysis of PAM4 designs as defined in emerging standards such as IEEE 802.3bs/cd and OIF-CEI-56G/112G. The company also demonstrated EEsof ADS 2017 signal-integrity channel simulation combined with N8844A data-analytics software to quickly and easily compare simulation results with measured data.
The company also reported that its Physical Layer Test System (PLTS) 2017, including the addition of PAM4 eye diagram testing, offers significant capabilities with regard to manufacturing test of high-speed interconnects. Furthermore, the company said, the new S93011A PNA-TDR software offers digital signal-integrity engineers a one-box solution for characterizing high-speed serial interconnects. In addition, Keysight said its EEsof ADS 2017 includes a new ElectroThermal simulator for PIPro, which provides a complete solution for the power integrity (PI) workflow, such as DC IR drop, DC electrothermal, and PDN impedance analysis.
Connectivity
TE Connectivity reported that it showcased OSFP and QSFP-DD connectivity products that will soon enable 400 Gigabit Ethernet in a range of datacenter devices. Targeted for massive aggregation of data across an array of applications, 400 Gigabit Ethernet (GbE) has completed the standardization process and was published in December 2017 by the IEEE 802.3bs Ethernet Working Group. Development of new and faster electrical and optical signaling technologies is simultaneously underway across the ever-expanding Ethernet ecosystem, the company said.
TE described the QSFP form factor as today’s industry workhorse for delivering 40 and 100 GbE. The Q is for quad—a nod to the four-channel electrical interface, with each lane running at 25 Gb/s for 100 GbE, the company explained. TE’s QSFP-DD connector adopts the same basic concept as its predecessor, but doubles the electrical contact density, via eight differential pairs capable of 50 Gb/s each, to achieve 400 GbE while allowing existing QSFP modules to be plugged into the same cage. The OSFP form factor is designed for maximum thermal and electrical performance but does not provide backwards compatibility to existing form factors without an adapter. The O is for octal—it is being designed to use eight electrical lanes to deliver 400 GbE—and SFP is for “small form factor pluggable.”
In addition, TE and Credo Semiconductor, a provider of mixed-signal semiconductors for the datacenter, enterprise-networking, and high-performance-computing markets, announced they had teamed up to demonstrate 112 Gb/s over a chip-to-module I/O channel and over a backplane channel. The demonstration employed TE’s OSFP I/O connector operating over a 10-inch PCB channel. The channel was driven by Credo’s 16-nm 112G PAM4 SerDes, operating over a total ball-to-ball channel loss of >15 dB. The demo showed bit error rate (BER) performance of better than 1×10-7.
High-speed connector
Also addressing interconnect at DesignCon was Molex. The company highlighted products such as the Impulse orthogonal direct backplane connector system and BiPass I/O and backplane cable assemblies, predicted in our January article.1 In addition, Molex reported that it highlighted its NearStack high-speed connector system and cable jumper assemblies (Figure 2), which use twinax cables to deliver a PCB alternative with superior signal integrity and low insertion loss while enabling implementation of 56 Gb/s NRZ and a path to 112 Gb/s PAM4.
Courtesy of Molex
The company also showcased its Impel Plus cabling system, emphasizing its backbone functionality within the Open19 Project,2 which defines a common form factor for servers, Tier-0 switches, and power shelves with a base internal cage system that can be implemented into a standard 19” rack solution. Delivering lower costs and reliable signal integrity from the switch to server with a robust connector to cable interface, the Molex Impel Plus cabling system achieves data rates up to 50 Gb/s PAM4 to create 100-Gb/s connectivity per server with the Open19 solution, the company reported.
In addition, Molex highlighted its high-density blind-mating optical backplane connectors for card, sled, and drawer applications that incorporate multifiber MT and VersaBeam expanded-beam MT ferrule technology, enabling the deployment of optical I/O based hardware. By utilizing Molex FlexPlane and Routed Ribbon solutions, system architects are able to manage onboard optical fiber counts that range from hundreds to thousands of fibers, the company reported.
Engineering award
Finally, DesignCon organizers announced the winner of the event’s Engineer of the Year Award: Dr. Mike Peng Li, Intel Fellow and the technologist for high-speed I/O and interconnects in the Programmable Solutions Group at Intel Corp. The Engineer of the Year Award recognizes elite ability and accomplishments in engineering and new product advancements at the chip, board, or system level, with a special emphasis on signal integrity and power integrity. As this year’s winner, DesignCon will bestow a $10,000 grant to the educational institution of Dr. Li’s choice in his name. The award was presented on Thursday, Feb. 1, at DesignCon.
“The Engineer of the Year Award recognizes an individual who has made substantial contributions to the field of engineering, and we are happy to recognize Dr. Mike Peng Li for his lifelong commitment to supporting innovation and discovery in this field,” said Naomi Price, conference content director at UBM, the event organizer. “Throughout his illustrious career, Dr. Li has continually pushed the envelope on industry standards across multiple topics, including Ethernet and PCI Express, and is an extremely deserving recipient of this award.”
“DesignCon has emerged as one of the primary technical conferences on signal integrity and high-speed I/O for chips, boards, and systems over the years and I am honored to receive such acknowledgement,” said Dr. Li.
The DesignCon 2019 conference is scheduled for Jan. 29-31, 2019, in Santa Clara, with the exposition being held Jan. 30-31.
References
- Nelson, Rick, “Software and instruments chase blazingly fast signals,” EE-Evaluation Engineering, Jan. 20, 2018, p. 12.
- Bachar, Yuval, “Open19 in 2018,” Open19 Foundation, Jan. 17, 2018.
