This eBook is part of the Library Series: Analog, Test & Measurement, and EDA and PCB Technology.
Timing isn't hard, you just need to stay on the clock. Which clock and how it's synchronized can be a challenge, especially when multiple sources are involved and tight timing constraints are imposed due to frequency, jitter, and the length of transmission lines. Multi-source clock-tree synthesis is an option for clock distribution, joining conventional clock-tree synthesis and clock mesh that's being utilized in more advanced designs. This and other topics like the difference between jitter and noise provide insight into system clock design and distribution.
Members can download our eBook that contains these articles covering clocks and timing issues: