Agilent Validates 3G SerDes Core

Agilent Technologies has validated its third-generation SerDes core in a 90nm CMOS process technology. Due to the core's good noise immunity, modular design and low power consumption, storage and networking OEMs are now able to embed as many SerDes channels (each operating at up to 6.25Gb/s) as needed onto a single ASIC chip.

"Our latest 90-nm validated SerDes core offers customers the flexibility to embed hundreds of SerDes channels on a single chip," said Kin Chan, director of engineering for the Networking Solutions Business Unit in Agilent's Semiconductor Products Group.

In tests conducted at Agilent, the embedded SerDes ASIC achieved error-free transmission driving signals over FR4 material (at room temperature) a distance of 76 centimetres (30 inches) using two connectors.