55nm process cuts power, die cost

Hsinchu, Taiwan: The 55nm process technology developed by Taiwan Semiconductor Manufacturing Company (TSMC) is a 90% linear-shrink process from 65nm, including I/O and analog circuits. The company claims that the process delivers significant die cost savings from 65nm, while offering the same speed and 10% to 20% lower power consumption.

Because the 55nm process is a direct shrink, IP providers can use existing libraries and port their 65nm designs with minimal work. The 55nm logic family includes general-purpose and consumer platforms.