Siemens Unveils Software Tool to Simplify and Speed Up Testing for Analog ICs

Siemens Digital Industries Software introduced a new tool called Tessent AnalogTest that helps simplify and accelerate the testing of analog and mixed-signal circuits — a long-standing bottleneck in chip development.

The tool can automatically create design-for-test (DFT) circuitry with minimal impact on performance for virtually any analog block, said Siemens. It also creates digital test patterns that are able to be deployed in days rather than months.

By integrating both capabilities into the analog design process, the EDA giant said it enables up to 100X faster testing of analog circuits. In turn, it significantly reduces costs and shortens time-to-market, particularly for complex chips used in areas such as automotive, medical, industrial, and the data center.

Testing is a critical phase of chip manufacturing, but it’s becoming important in analog and mixed-signal chips, where defects are often hard to detect. Even a single fault can degrade performance or cause the chip to fail.

In contrast, digital chips are specifically designed to be tested: Test circuits are integrated in the silicon in a process called DFT. These ports enable automated test equipment (ATE) to run test programs on chips called automatic test pattern generation (ATPG) to make sure everything works inside the chip.

But building these test circuits into analog chips is a time-consuming and expensive endeavor. According to Siemens, Tessent AnalogTest is the first commercially available tool to solve the issue by placing them automatically in analog circuits.

"This pioneering software offers rapid test outcomes while delivering higher analog defect coverage and up to 100X faster tests compared to conventional methods," said Ankur Gupta, SVP and GM of the digital design business within Siemens’ EDA unit. "Tessent AnalogTest software represents a monumental leap forward in addressing key quality and cost challenges associated with analog circuit testing, enabling our customers to streamline processes while reducing overall test costs.”

The Rising Stakes and Complexity of Analog Testing

Mixed-signal ICs are becoming make-or-break parts in sectors such as medical, industrial, automotive, and data centers. They handle critical functions — e.g., power management, data conversion, and wireless and wired communication — and they’re growing both in scale and complexity.

Digital logic is increasingly placed close to analog and power blocks in ICs to boost performance and flexibility, adding to the testing challenges. Analog blocks are also being embedded within larger SoCs such as AI accelerators and RF transceivers.

In data centers, for instance, multiphase controllers are emerging as one of the core building blocks of the DC-DC converters. These ICs are used to control the smart power stages placed at the point of load (POL) to regulate the power rushing into CPUs, GPUs, and AI SoCs, playing a key role in improving power and thermal efficiency.

Today's AI chips tend to be co-packaged with high-bandwidth memory (HBM) to enable faster data movement in data centers. The 3D-stacked DRAM contains a logic die deeply intertwined with mixed-signal circuits such as PHYs.

In electric vehicles and renewable-energy storage systems, battery-management ICs are being upgraded to enable faster charging and maximize usable capacity without risking overheating and/or degradation. These chips are also equipped with analog to-digital (ADC) converters to more accurately track voltage, current, temperature, and other characteristics at the cell and pack levels, which are used to estimate the battery’s remaining runtime as well as its lifespan.

In industrial automation, analog front ends (AFEs) are becoming a core building block on smart factory floors. Used to convert and condition analog signals from sensors embedded in robotics and other machinery, the latest chips are highly flexible and even software configurable. They’re designed to deliver the speed and accuracy required to adapt equipment to changing operating conditions as well as identify potential malfunctions in machinery before it breaks down.

However, testing the analog blocks in these chips remains a technically demanding task. The analog circuits are fundamentally more difficult to deal with due to the fact that they process continuously varying signals such as voltage, current, and frequency.

Every nuance in one of those signals or a small amount of noise can alter the performance of the device in the real world. In addition, analog devices can take a long time to reach a stable output or “settle” after the input changes.

Testing mixed-signal circuits adds another level of complexity because analog and digital blocks share the same slab of silicon. Noise due to the digital circuitry will negatively impact the performance of the analog.

Capturing and understanding all of these complexities is the core of the challenge, said Etienne Racine, product manager of Tessent at Siemens EDA. As a result, analog testing is traditionally a painstaking process, often requiring engineers to integrate custom test circuitry into the chip and then prolonged coding to create and run the large number of tests required by analog. It’s also necessary to use expensive mixed-signal equipment to test the functional specifications.

“Obviously, companies want to reduce test time, but there is not much room left to improve digital test times,” said Racine. “Thanks to years of digital scan technology improvements, test time for the digital portion of an IC might be hundreds of milliseconds, but many seconds for the analog portion. That’s a big challenge right there.”

Analog DFT Closes the Gap with Digital DFT

While testing analog circuits has long lagged behind digital in terms of speed and scalability, Siemens said Tessent AnalogTest closes the gap by automatically creating the internal test circuits and the corresponding tests. The solution enables testing with digital test equipment instead of more expensive mixed-signal equipment, and these tests can run in less than a millisecond.

Part of the company’s broader Tessent silicon lifecycle solution, the AnalogTest tool “implements a digital scan-based test that completes up to 100X faster than conventional specifications-based tests,” noted Racine. “In other words, it brings the same benefits that digital logic has enjoyed for many years with scan and ATPG to analog circuits and designs.”

When paired with the company’s Tessent DefectSim technology, Siemens said the improvements enable chip designers to test for a wide range of potential defects — translating to more than 90% defect coverage —  in analog circuit blocks. Engineers can run through these tests in a matter of hours instead of days, sharply reducing their time-to-market.

“The primary interest,” said Racine, “is reducing test time without reducing quality, so it benefits any segment that has high volumes, such as consumer electronics and automotive.”

The software can also be used to double-check defect coverage in simulation up to 100X faster than current technologies. These pre-silicon simulations make sure that the physical chips can be tested against industry standards such as ISO 26262 for automotive safety.

The AnalogTest solution is already being put to use. With the tool, onsemi said it was able to achieve more than 95% analog defect coverage on a taped-out design and reduce test times by more than 100X compared to existing approaches.

onsemi SVP of New Product Development Steven Gray said one of the main bottlenecks in analog and mixed-signal chip development is the lack of EDA tools for DFT. “Tessent AnalogTest is a tool that makes it practical to automatically generate analog DFT solutions and associated tests. Through our collaboration with Siemens as an early partner, we are optimistic that this methodology will result in shorter development times, much faster tests, and better quality, similar to how scan improved DFT and test for digital circuits.”

Early partners are already using Tessent AnalogTest; it will be generally available in late 2025.