The JESD204 Story
As converter resolution and speed ramped up, designers needed a more efficient interface, which led to the creation of JESD204. This is a 12-part series about JESD204 about the protocol and how it will change how we design.
More articles will be added in the near future, and a PDF version will be available for download when the series is complete. Here is what we have so far:
- What Is JESD204 and Why We Should Pay Attention to It?
- High-Speed Converter Survival Guide: Digital Data Outputs
- JESD204B vs. Serial LVDS: Interface Considerations for Wideband Data Converter Apps
- Critical Design Issues for a Functioning JESD204B Interface
- Synchronizing Multiple ADCs Using JESD204B
- Three Key PHY Performance Metrics for a JESD204B Transmitter
- The ABCs of Interleaved ADCs
- Overcoming Verification Challenges for High-Speed Data Converters
- Slay Your System Dragons with JESD204B
- An Intro to JESD204B Subclasses and Deterministic Latency (Part 1)
- An Intro to JESD204B Subsclasses and System Considerations (Part 2)
- Interfacing FPGAs to an ADC's Digital Data Output