UARTs Minimize CPU Bandwidth Needs

Aug. 1, 1998
Minimal CPU bandwidth requirements and increased system throughput are the goals of the XR16C850 (single) and XR16C854 (quad) UART ICs with on-chip transmit and receive FIFO counters as well as 128-byte FIFO depth for receiving longer data packets.

Minimal CPU bandwidth requirements and increased system throughput are the goals of the XR16C850 (single) and XR16C854 (quad) UART ICs with on-chip transmit and receive FIFO counters as well as 128-byte FIFO depth for receiving longer data packets. Applications are expected to include networking equipment such as routers, remote access servers, hubs and ISDN modems as well as PC serial communication cards and various industrial automation equipment.The chips provide a maximum 1.5-Mbps data rate at 5V. For industrial equipment, both have an automatic RS-485 half-duplex switch.

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