Communications: Phase-Locked-Loop Hard Macros Shed 2/3 Of Their Required Area

Sept. 20, 2004

Hard macros for phase-locked loops (PLLs) are now available as intellectual property (IP). The PLL IP macros take up typically about one-third the physical area of the company's standard PLL products without sacrificing any performance. The macros occupy just 0.07 mm² when implemented in 130-nm design rules. This area includes the dividers and other digital support logic, supply bypass capacitors, and block isolation. Each PLL includes the company's LockNow! technology, which can significantly boost lock times. The hard macros are available for a per-use license fee with no royalty fees. Deliverables include GDSII and LVS Spice netlists, behavioral and synthesis models, library exchange format files, and full documentation.

True Circuits Inc.www.truecircuits.com/tci_technology.html

About the Author

Dave Bursky

Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.