Transceiver Core Hits 2.5 Gbps

For use in CMOS ASICs, the 2.5 Gbps serializer/deserializer (SERDES) ASIC core provides four times the bandwidth of other CMOS ASIC SERDES cores and provides a level of ASIC integration not possible with other high-speed technologies such as GaAs and bipolar. This core is designed for networking, telecommunications and workstations. This core offers the possibility of building switch/routers with an order-of-magnitude increase in bandwidth over existing switch/routers without the need for discrete SERDES and ASIC packaging with thousands of pins. Switch architectures with at least 512 Gbps are possible by integrating high-speed SERDES to a crossbar architecture.