10-Gb PHY Transceiver Built Using SOI-CMOS Technology

Debuting as the market’s first 10-Gb Ethernet physical-layer large-scale integration (LAN-PHY LSI) transceiver designed using a combination of silicon-on-insulator and complementary metal-oxide semiconductor (SOI-CMOS) technologies, the M69850 integrates XGXS, PCS and PMA functions on a single chip that operates from a single 1.8V supply. Incorporating serializer/deserializer, phase-locked loop, clock data recovery, transmitter/receiver elastic FIFO, 8- to 10-bit encoder/decoder, 64- to 66-bit encoder/decoder, and gearbox functions, the XGXS, PCS and PMA blocks provide data conversion between the 10.3-Gb PMA and 3.125-Gb XAUI interfaces. In addition, an XAUI-PMD interface with a differential, ac-coupled interface reduces power consumption, while an MDIO interface ensures IEEE802.3ae compatibility. (SOI-CMOS technology is said to provide faster transistors for better performance and less substrate noise for lower jitter level; it is also credited with preventing latch-ups.). Other features of the LAN-PHY LSI chip include: either a 156.25-MHz, voltage-controlled oscillator or 156.25- or 644.53-MHz external reference clocks; comma detection and byte alignment; de-skewing and channel-to-channel alignment functions; and a built-in PRBS pattern generator. Available in a 289-pin BGA package and targeted for use in local and metropolitan area networks (LANs and MANs), the M69850 SOI-CMOS chip is priced at $300 each in sample quantities. For more details and volume pricing, contact MITSUBISHI ELECTRIC & ELECTRONICS USA INC., Electronic Device Group, Sunnyvale, CA. (408) 774-3191.