Claimed as the industry’s highest-performance and most highly integrated chipset for packet processing and traffic management, the TeraPacket chipset targets line cards in Internet routers, multiservice switches, and metropolitan switches used in edge and core networks. The chipset consists of the Multi-Service Packet Engine (MPE) and Multi-Service Traffic Manager (MTM) and provides speeds of 40 Gbps, 20 Gbps or 10 Gbps. The 40 Gbps performance and high integration of the TeraPacket chipset enable engi-neers to design a line card with four OC-192 ports, four 10 Gbps Ethernet ports, or sixteen OC-48 ports. This integration is said to achieve a 65% reduction in the cost and 63% reduction in the power consumption of line cards. Performance is achieved via a hardwired yet configurable architecture in which all the functions and protocols are implemented in high-speed silicon. A 40 Gbps, full-duplex solution consists of two TN400 MPEs and two TN401 MTMs; a 20 Gbps, full-duplex solution consists of one TN200 MPE and one TN201 MTM; and a 10 Gbps, full-duplex solution consists of one TN100 MPE and one TN101 MTM. The chipset is designed to handle all the major communication protocols, including IPv4, IPv6, ATM, Frame Relay, PPP, Ethernet, MPLS, and MPLS Martini Draft. The devices collect a full range of network statistics in all their applications. The TeraPacket chipset family is sampling in December, with production scheduled for early 2003. All devices will ship in a FC-BGA package. Pricing for 10,000-unit quantities ranges from $1,250 to $2,600 for the MPEs and also for the MTMs. A full range of development tools is available. TERADIANT NETWORKS INC., San Jose, CA. (408) 519-1726.
Company: TERADIANT NETWORKS INC.
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