TSMC and Cadence Collaborate On 65-Nanometer Wireless Design Technologies

Cadence Design Systems Inc. and Taiwan Semiconductor Manufacturing Company (TSMC) collaborated in producing a new TSMC 65-nanometer RF process design kit (PDK) compatible with the Cadence Virtuoso custom design platform. The companies also develope downloadable RF, analog and mixed-signal (RF and AMS) design-flow demonstration packages for wireless designers. The new TSMC 65-nanometer RF PDK and Cadence RF and analog design flow support the Cadence Virtuoso IC design platform. The demonstration packages contain TSMC 65-nanometer RF-enabled design examples for RF and AMS block creation, application notes and methodology documentation, and a design example-circuit database with complete execution scripts and flow. "With this collaboration, wireless chip designers now have a comprehensive set of interoperable design tools, methodologies and process technologies necessary to achieve shorter, more predictable design cycles for highly integrated, 65-nanometer RF and AMS designs," Kuo Wu, deputy director of Design Service Marketing at TSMC, said in a statement. The new Virtuoso IC based 65-nanometer RF PDK and TSMC's Nexsys 65-nanometer LP standard cell library can be downloaded from the TSMC Web site.