InP-Based Chipset Architecture Eyes OC-768 Systems

A new chipset architecture, which combines indium phosphide (InP) and CMOS components, is targeting OC-768 systems. The architecture is designed to enable long-haul equipment suppliers to build high-performance 43 to 50 Gb/s linecards and to allow module manufacturers to develop cost-competitive solutions for short reach and metropolitan applications at 40 Gb/s. The chipset architecture interfaces the higher-level system functions such as SONET framing to the physical layer components, enabling electrical-to-optical and optical-to-electrical conversion. In the process, a 16-bit data bus operating at a data rate between 2.5 and 3.125 Gb/s is converted to a high-speed serial stream operating between 40 and 50 Gb/s. On the system side, a CMOS 16:4 mux and a 4:16 demux provide skew compensation logic required to support the upcoming OIF SFI-5 standard. These CMOS components also include critical management functions such as real-time diagnostics, testability and fault isolation.On the line side, the architecture incorporates a 4:1 mux with an integrated clock-multiply unit and a 1:4 demux with integrated clock and data-recovery circuitry, both of which are designed in InP. The InP technology provides sufficient gain to drive the optics and enables rise and fall times of 8 ps with very low jitter of less than 1 psRMS. The architecture was developed with standard power supplies in mind to fit standard 300-pin MSAs. For further information and price, call INPHI CORP., Westlake Village, CA. (805) 446-5100.