Chipset Designed Using Scalable Non-Blocking STS-1/AU-3 Architecture
Claiming to set new benchmarks for aggregating, grooming and transporting 2.5-Gb/s and 10-Gb/s metro services, the CHESS-III chipset includes the PM5376 TSE-Nx160 STS-1/AU-3 cross-connect device and PM5326 ARROW-2x192 and PM5324 ARROW-1x192 SONET/SDH