LAN Switch Eliminates Redundant PHY Chip

March 31, 2003
Advances in notebook technology create a thirst for new features and increased functionality, culminating in greater cost and shrinking space. One solution to the cost/space issues is to use a wide-bandwidth analog local-area network (LAN) switch that...

Advances in notebook technology create a thirst for new features and increased functionality, culminating in greater cost and shrinking space. One solution to the cost/space issues is to use a wide-bandwidth analog local-area network (LAN) switch that multiplexes Ethernet dynamic signals between a notebook and its docking station.

Historically, a notebook and its docking station each contained a physical-layer (PHY) transceiver and an Ethernet controller. Each set interfaced with the host via the PCI bus—a redundant set in the notebook and one set in the docking bay itself (Fig. 1). Eradicating redundancy from products is a top priority for today's notebook manufacturers. Removing an extra PHY transceiver and Ethernet controller in the docking bay can reduce the Ethernet device cost by up to 43% and free up space.

To remove expensive chips from the Ethernet connection, notebook manufacturers can use a wide-bandwidth analog LAN switch configured as a quad, single-pole, double-throw (SPDT) analog switch (Fig. 2). SPDT LAN switches eliminate the PHY and Ethernet controller from the notebook's docking station. This is accomplished by multiplexing between the RJ-45 connectors on the notebook and the docking station.

On the notebook side, the PHY transceiver and Ethernet controller remain connected to the PCI bus, while the SPDT analog LAN switch routes signals between the RJ-45 connector's isolation magnetics and the docking station. The docking bay's select pin, or an internal logic function, controls the direction of the LAN switch.

While cost and space savings are important goals, designers shouldn't ignore problems with high-speed transmission lines and the changing landscape of Ethernet protocols. The IEEE 802.3 standard mandates that each Gigabit Ethernet (1000-Mbit/s) twisted-pair transmission line run at 250 MHz (125 MHz per line), as opposed to traditional 10/100 Ethernet's 50 MHz per twisted pair.

Gigabit Ethernet must also have four bidirectional twisted-pair transmission lines, instead of the traditional two unidirectional twisted-pair transmission lines. Because both Gigabit Ethernet and traditional Ethernet implement the same concept of routing from the docking bay to the notebook PC, Gigabit Ethernet can eliminate a duplicate PHY transceiver and Ethernet controller by using two quad SPDT analog LAN switches.

Yet going from 50 to 125 MHz per line and bidirectional transmission lines could pose a problem for some analog LAN switches. If the switch's bandwidth isn't high enough, or the −3-dB frequency roll-off point is less than the input signal frequency, then the switch will attenuate the signal. Similarly, if the on-resistance and on-capacitance are too high for the capabilities of the PHY, designers may have problems with driving and receiving on the transmission lines. These design challenges can be eliminated by selecting an Ethernet LAN switch that offers greater than 125 MHz of bandwidth, rail-to-rail signal handling, and on-resistance and on-capacitance.

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