Communication Controller Supports Time-Triggered Protocol

This next-generation TTP/C communication controller supports time-triggered protocol (TTP) and offers up to 15 Mb/s data rate. The chip is designed to meet the TTP/C specification and can be transferred to silicon as a stand-alone device or as part of a system-on-chip (SoC) solution. The C2 and the C2S models allow communication at speeds up to 5 Mb/s in asynchronous mode and 25 Mb/s in synchronous mode. The configurable bus interface module affords 8-, 16-, or 32-bit width, and either Intel or Motorola-type accesses.
The CNI (Communication Network Interface) SRAM memory is configurable and supports dual-port access from both the host CPU and the TTP/C communication controller. Configuration information for the TDMA round layout, operating modes and clock synchronization parameters are stored in the MEDL (Message Descriptor List), which is typically implemented in either a flash or SRAM area.
Both the C2 (part# AS8202) and the C2S (part# AS8202S) versions are qualified for automotive applications. A stand-alone controller, based on the TTP/C-C2S and supporting the full 32-bit host CPU bus, is also available.