SerDes Chipset Integrates Unique Clock Architecture

Oct. 8, 2008
Forming a high-speed LVDS serializer/deserializer (SerDes) chipset, the DS90UR241 serializer and DS90UR124 deserializer employ a true embedded clock architecture, eliminating the need for a second oscillator, and a unique random data lock feature. The

Forming a high-speed LVDS serializer/deserializer (SerDes) chipset, the DS90UR241 serializer and DS90UR124 deserializer employ a true embedded clock architecture, eliminating the need for a second oscillator, and a unique random data lock feature. The chipset serializes 24 bits of data over a single differential pair at a rate of 1.03 Gb/s. Its random data lock feature enables quick recovery from data-stream disruptions caused by spurious electrical impulses or momentary mechanical disconnects. Other features include ac coupling, at-speed BIST link diagnostics, programmable pre-emphasis, operating frequency from 5 MHz to 43 MHz, dc-balanced transmission, voltage range from 3V to 3.6V, and a temperature range from -40°C to +105°C. The DS90UR241 comes in a 48-pin TQFP and the DS90UR124 in a 64-pin TQFP with prices of $6.60 and $7 each/1,000, respectively. NATIONAL SEMICONDUCTOR CORP., Santa Clara, CA. (800) 272-9959.

Company: NATIONAL SEMICONDUCTOR CORP.

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