Quad SerDes Chip Integrates Clock-Jitter Cleaner

Allowing designers to implement various communications standards with one device, the TLK3134 four-channel serializer/deserializer chip integrates a reference clock jitter cleaner to ease the design process and allow the use of an economical reference clock source. The chip enables high-speed, bi-directional, point-to-point data transmission at rates up to 30 Gb/s. Configurable as either a XAUI or 10 GFC transceiver, it supports a data bandwidth range from 600 Mb/s to 3.75 Gb/s per serial lane and meets CPRI and OBSAI specifications for wireless infrastructure equipment. Other features include support for independent channel SerDes operation modes in both eight- and 10-bit data modes (TBI and eight-bit + control), support for 10 GbE (XAUI), 1X/2X/10X Fibre channel, CPRI (x1/x2/x3), OBSAI (x1/x2/x4), and 1 GbE (1000 Base-X) data rates, a 10 GbE XGXS (XAUI) compliant core, and 1000 Base-X PCS support. Available in a 289-pin BGA package, price for the TLK3134 is $35 each/1,000. TEXAS INSTRUMENTS INC., Dallas, TX. (800) 477-8924.