Faster processors and complex mobile devices are severely straining the ability of ICs to deliver the desired performance. As chip designs scale below 40 nm and into the 28-nm range, yields are suffering because of the extreme leakage effects on the wafer. Wafer processing companies can still make traditional MOSFETs in a scaled-down planar configuration down to about the 20-nm node, but yields decrease.
Soitec’s fully depleted (FD) silicon wafers promise to solve the leakage problem. They use silicon on insulator (SOI) technology, which places a super-thin FD layer on the surface of the wafer to provide a barrier that significantly reduces the leakage, leading to higher yields and greatly improved performance. Chips can run at higher speeds and frequencies with less power consumption. The FD approach is proving so successful that it is now part of the semiconductor industry’s International Technology Roadmap for Semiconductors (ITRS).
A standard FD planar MOSFET is formed on top of the undoped fully depleted top layer of the wafer. Soitec controls the thickness to within 5 angstrons. Using the FD wafers, conventional CMOS can scale down to 20 nm using existing intellectual property (IP) and getting profitable yields. Supply voltages, then, can scale down to 0.6 V with awesome savings in power. This lower power consumption can lead to major consumer benefits like four more hours of browsing, two and a half more hours of HD video, two hours of HD video recording, or an extra full day of use on the typical smart phone.
To get even smaller feature sizes, a unique FinFET design where the FD top layer becomes part of the transistor is gaining support. Source and drain are closer together and formed with implants. The gate wraps around the structure. This “vertical” design throws out all the previous IP, meaning chips have to be redesigned with the new devices. While that’s expensive, it allows processes to get down to about 10 nm with even further improvements to performance. And that’s not all. The new vertical FinFET requires significantly (20% to 25%) fewer process steps, further boosting yields and profits.
While no one is currently using the FinFET design, there’s no doubt it will be on the roadmap of many chip companies as they face the growing difficulty of maintaining Moore’s law. Again, physics and superior wafer designs are letting us achieve the high speed and lower power consumption required to implement new, faster Long-Term Evolution (LTE) cell phones and tablets.
For more, see “Move Over, Moore’s Law—Here Comes 14 nm."
