3.6-Gsample, 12-Bit ADC Revolutionizes SDR Designs

July 7, 2010
12-bit ADCs sample at 3.6 GSamples/second making software-defined radio and other communications applications easier to implement.

Independent channels

One factor always seems to constrain the latest software-defined radio (SDR) designs: digitizing speed. Ever-climbing speeds delivered by analog-to-digital converters (ADCs) still doesn’t seem to be enough.

A temporary solution may be on the way, though, with what National Semiconductor Corp. claims is the fastest 12-bit ADC. At 3.6 Gsamples/s, the ADC12D1800 is 3.6 times faster than any other available 12-bit device, according to the company. It also offers a dynamic performance of –147-dBm/Hz noise floor, 52-dB noise power ratio (NPR), and –61-dBFS intermodulation distortion (IMD).

In addition to the ADC12D1800, NSC introduced two other members to the family: the 3.2-Gsample/s ADC12D1600 and the 2.0-Gsample/s ADC12D1000. Design targets for these ADCs include wideband basestations, radar, military communications, multichannel set-top boxes (STBs), signal-intelligence, and light detecting and ranging (LIDAR) applications. The ADCs employ a unique folding flash architecture. Standard flash converters with folding circuitry lessen the number of comparators needed, which accelerates sampling.

In addition to the 3.6-Gsample/s rate, the ADC12D1800 provides dual-channel rates up to 1.8 Gsamples/s.Other specifications includea 57.8-dB signal-to-noise ratio (SNR), 67-dBc spurious-free dynamic range (SFDR), and 9.2 effective number of bits (ENOB) at 125 MHz. It consumes only 2.05 W per channel.

The ADC12D1600 delivers single-channel sampling rates up to 3.2 Gsamples/s and dual-channel rates up to 1.6 Gsamples/s, as well as the single-channel 3.2-Gsample/s rate.It features a –147.5-dBm/Hz noise floor, 52-dB NPR, and –63-dBFS intermodulation distortion (IMD). Furthermore, it consumes 1.9 W per channel and offers 58.6-dB SNR, 68-dBc SFDR, and 9.3 ENOB at 125 MHz.

The 2.0-Gsample/s ADC12D1000 also delivers dual-channel rates up to 1.0 Gsample/s.It features a –147.5-dBm/Hz noise floor, 52-dB NPR, and –66-dBFS IMD. The device, which consumes 1.7 W per channel, has a 59.1-dB SNR, 70.5-dBc SFDR, and 9.5 ENOB at 125 MHz.

All of these 12-bit ADCs are supplied in a leaded or lead-free, 292-ball, thermally enhanced ball-grid-array (BGA) package. They also are pin-compatible with their forerunners, the ADC10D1000 and ADC10D1500. They run off a 1.9-V single supply and consist of two channels that can operate interleaved or as independent channels (see the figure).

Circuitry is included for multi-chip synchronization, programmable gain, and offset adjustment per channel. The internal track-and-hold amplifier and extended self-calibration scheme enable a very flat response of all dynamic parameters for input frequencies exceeding 2 GHz, while providing a low 10–18 code error rate.

Entirely new SDR architectures can be realized with the ADC12D1x00 family due to its ability to accurately receive modulated, band-limited signals within a large bandwidth. In military radar systems, a single ADC12D1X00 combined with a digital downconverter can replace multiple mixers, filters, amplifiers, and local-oscillator stages used in traditional heterodyne double- or triple-conversion radio implementations.

Another perhaps unforeseen solution involves next-generation multi-channel STB applications. One ADC12D1x00 can replace all of an STB’s tuners. Shifting such architectures to an SDR implementation dramatically reduces board area, power consumption, and cost, while improving system flexibility.

All three ADCs are sampling now, with production quantities available in the third quarter. For more information on the ADC12D1800’s pricing, samples, and reference board, go to www.national.com/pf/DC/ADC12D1800.html.

National Semiconductor

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