SmartNICs are designed to provide efficient, low-latency processing of network traffic to offload host processors. Many SmartNICs employ FPGAs to handle this type of work. However, programming an FPGA is no easy task, and neither is configuring a SmartNIC.
I talked with BrnoLogic’s CTO, Lukas Kekely, about the new DynaNIC solution, which works on platforms from companies like AMD, BittWare, napa:tech, Prodesign, Reflex CES, and Silicom (Fig. 1). DynaNIC is designed for developers who want to deal with software while BrnoLogic handles the hardware.
DynaNIC can be configured to manage the entire data flow, from the incoming SerDes to the outgoing interface (Fig. 2).
The platform can handle write speeds up to 400 Gb/s. It utilizes the Data Plane Development Kit (DPDK) API that’s the de facto standard for SmartNICs. All of the FPGA configuration and support is taken care of, allowing developers to work at the software level to configure and access the SmartNIC.
DynaNIC can be configured to extract data from anywhere in the flow (Fig. 3). The FPGA pipeline supports the open-source RTE Flow API from DPDK. It’s easy to set up header field extraction and parsing. The modular architecture works with raw processing speeds from 100 Gb/s to 1 Tb/s, depending on the hardware.
The SmartNIC solution can be used to implement IDS/IPS services, firewalls, and anti-DDoS solutions in addition to routing and switching. Multiple, reusable blocks can be configured to handle different stream processing requirements.