Motoring Up the Evolutionary Highway

May 24, 2006
How will motor-control system designers take the next evolutionary step toward improving drive characteristics?

Certain electronics markets continually experience giant leaps in innovation. For others, like motor control, the market evolves at more gradual pace. But you can’t deny motor technology’s durability: It’s been around for more than 100 years, with many of the earliest motor types still in use today.

One of the main challenges faced by developers is finding the next evolutionary step to improve drive characteristics. When designing motor-control systems, developers focus on achieving the best quality and performance of the control mechanism. Microcontroller development has enabled gradual improvements to be made, ranging from adding quality peripherals through to devices that heighten characteristics such as interrupt response, maximum revs per minute, acceleration speed, and torque control.

The latest microcontrollers, such as Renesas’ SH7201, offer developers a solution that could take them toward the next step in motor performance, precision, and quality (Fig. 1).

CPU core with floating-point unit

MCU devices for motor-control applications now feature a superscalar CPU core with twin pipelines and a floating-point unit (FPU) capable of supporting both single- and double-precision floating-point operations. Superscalar Harvard architectures offer developers the ability to execute two instructions simultaneously every clock cycle. The FPU easily handles the complex mathematical control algorithms. Devices are typically able to handle single and floating- point operations, and they offer four-cycle execution of basic FPU operations.

Evolving the instruction set and addressing modes of established CPUs, these devices have improved with the addition of bit instructions for more efficient bit manipulation.

The new CPU features a new register—the TBR, or jump table base register. Such a register will store the address of a function pointer table. This facilitates function calling anywhere in the 4GB address space, simply through the use of an 8bit offset to the TBR contained in a 16bit instruction op code. The net result is reduced code size and improved efficiency.

Delayed branch instructions are another handy feature supported by the latest devices. The nature of the CPU’s twin pipelines means that new instructions are taken before previous instructions are fully decoded. This means that the instruction after the branch was already loaded into the pipe. Rather than discard the instruction, it’s executed before the branch, even though it appears in the source code after the branch. It’s said to be in a “delay slot.” In many cases, no useful instruction can be placed in a delay slot, thus requiring the use of a NOP, which consumes valuable code space and a CPU cycle. The latest devices are able to eliminate this wasteful situation by branching without delay-slot instructions.

Particularly useful in motor-drive applications are CLIP instructions. These instructions compare the contents of a CPU register with upper and lower saturation values. If the results are above or below the saturation levels, the register contents are automatically reset to the defined values.

Keeping the CPU and FPU supplied with instructions and data is achieved via on-chip cache memory, which efficiently uses the bus controller’s support for SDRAM as well as conventional flash and SRAM memories (Fig. 2).


One useful peripheral found on the latest microcontroller units is the multifunction timer pulse unit 2 (MTU2). This peripheral provides six timer channels of 16bit resolution. Moreover, it includes general-purpose functionality such as buffered input capture and output compare signal generation, standard and reset-synchronised PWM generation, synchronised timer starting and stopping, and synchronised timer loading.

The MTU2 also has specialised features designed for motor control. For example, channels three and four can be used together to generate six output waveforms for three-phase complementary PWM with dead-time insertion. One of the problems when generating such waveforms is achieving duties close to 0% and 100%. The MTU2 achieves this through integral counters.

Although desired dead time is loaded into the MTU2, the characteristics of the switching transistors can mean that the dead-time set is overly conservative or the time is violated. Positional and speed information relating to a motor can be achieved by using the MTU2’s phase-counting mode. Here, the phase difference between two input clock signals determines whether the counter counts up or down, depending on which signal leads.

Microcontroller devices such as Renesas’ SH7201 are well-suited to controlling three-phase motors, particularly when it comes to complex algorithms, because these require high CPU performance (Fig. 3). The combination of superscalar CPU, floating- point unit, and multiple timers offer motor-control system developers a powerful solution, one that leads to the next evolutionary step in motor performance, precision, and quality.

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