Clock Driver Supports DDR SDRAMs

Supporting double data rate (DDR) synchronous dynamic random access memories (SDRAMs), the CDC857 phase-locked loop (PLL) clock driver circuit provides up to 10 low-jitter, low-skew differential clock signals at speeds up to 170 MHz. The clock driver lets designers build next-generation dual in-line memory modules (DIMMs) that support the PC200 and PC266 DDR-1 bus standards, yet allows them to make the transition to the even faster PC300 and PC333 DDR-II standards. Up to 10 differential PLL clock outputs from a single input allow driving multiple SDRAM loads, and LVTTL/CMOS inputs provide system flexibility in signal selection. Two versions of the device support 2.5V and 3.3V operation with power-down mode that disables the PLL during periods of low signal activity.