The analog-to-digital converter (ADC) segment is closely aligned with the overall drive to perform as much signal processing in the digital domain. The drivers and trends are similar to the pressures that affect the logic areas. Converters are moving toward more bits and higher speeds. In these areas, the drivers are parallel to the digital world, and they look to smaller feature sizes for higher levels of integration.
Unfortunately, the bypass capacitors are getting larger than the IC packages, so reducing space becomes more difficult. The increases in speed and data word resolution force converter makers to pay extra attention to power consumption and packaging. A revolutionary change in architectures is being driven by requirements for smaller and lower power. Some of these new designs will be possible to embed in larger chips as further building blocks.
While the high-end products focus on performance, the low- and middle-range products must address both performance and cost. The mid-range converter space, with converters with a sampling rate of 1 to 10 Msamples/s, usually resides in the 8- to 16-bit resolution level. The cost of this mid- or low-range converter is just as significant a parameter as its monotonicity or linearity.
Precision is adequate in the low-cost areas. To address the ever-changing needs of converter users, vendors are expanding their converter product portfolio. Their focus is on low power, smaller packages, and integrated references. ADCs need to convert as fast as possible, but faster converters are typically only necessary for the lower latency, not the higher speed. Most users want to complete the conversion and power the converter down to achieve an overall lower-power consumption figure.
For example, many users employ 200-ksample/s converters but only require 10- ksample/s data rates. Therefore, they can get a 98% reduction in operating power, compared to other "low-power" converters, by powering down between conversions. An addendum to the "sampled" samples is a growing need to perform data reduction or averaging before sending the data out.
Other important ADCs beyond just voltage inputs include voltage to frequency, frequency to voltage, and rms-dc.
The lower sophistication and experience of users means that vendors must do a better job of design and support. The customer is easily responsible for the system, but not expert in enough facets of the design to be good in everything. Smarter customers will rely on their semiconductor vendor(s) to take responsibility for the analog and special-purpose mixed-signal portions.
>POWER-SUPPLY VOLTAGES track the digital components. Lower supplies help the power consumption in the digital sections but make the analog sections more difficult.
>MORE "EXOTIC" SEMICONDUCTOR processes will be used in the search for higher speeds and lower power.
>ANALOG FRONT-END COMPONENTS will see increased integration. Putting analog-signal-processing components on-chip reduces the design effort and also improves signal quality.
>MORE INTEGRATION IS EXPECTED with digital post-processing functions. This level of integration reduces the processing load on the system processor or DSP, which also limits power consumption in the logic section of the system.
>SPEEDS ARE RISING. First, higher conversion rates reduce data latency and, with a gated sampling scheme, can reduce system power consumption. Plus, higher analog bandwidths let the system capture faster signals.
>INTEGRATED AVERAGING AND DATA REDUCTION FUNCTIONS will limit the loading of DSPs in a system. Processing in the analog domain helps slash latency and power consumption.
>LOWER POWER is becoming a necessity. While most analog subsystems aren't battery-powered, system power consumption is a serious design issue, particularly as the analog subsystems integrate more functions into a single chip and the packages shrink.
>SENSOR-SPECIFIC CONVERTER SUBSYSTEMS will become more popular. As analog knowledge slowly slips away from systems design groups, more of the analog subsystem will be integrated into a single package.
>OUTPUTS ARE MIGRATING from the parallel outputs to I2C and SPI (serial packet interface), as well as other serial interface structures. This change simplifies the design interfaces.