Often, it's necessary for a sensor system to compute the ratio of two capacitors. Doing so re-duces the transducer's sensitivity to dielectric errors from such factors as temperature. Furthermore, dual sensors are typically used to double the capacitance of CMEAS, while CREF may vary less than 1%. Thus, the transducer's accuracy is increased when implementing a circuit like the ratiometric state-variable oscillator of Figure 1.
Well suited for precision ratiometric capacitive-sensor applications, the oscillator's output frequency is proportional to the ratio of CMEAS/CREF (C3/C4). The oscillator was designed with a supply voltage of only 0.9 V, using the NCS2001 op amp and NCS2202 comparator.
Two integrators and a differentiator make up the circuit. Each integrator has a phase shift of 90°, while the differentiator adds another 180° phase shift. So, a total phase shift of 360° is fed back to the input of the first integrator to produce the oscillation.
The first integrator stage consists of amplifier A1, resistor R1, and capacitor C1, while the second integrator comprises amplifier A2, resistor R2, and capacitor C2. Resistor-capacitor combinations R1 and C1, and R2 and C2, set the gain of each integrator stage, plus the oscillation frequency. Amplifier A3, resistors R3, R4, and R5, and sensor capacitances C3 and C4 form the differentiator stage, which provides the 180° phase shift.
The values of R3, R4, and R5 are selected to set the break frequencies of the differentiator stage, so that the gain of the stage equals C3/C4 at the oscillation frequency. Also, R5 supplies a dc current path through capacitor C3 to initiate oscillation at power-up. Figure 2 shows a Bode plot of the differentiator stage.
A voltage-limit circuit prevents the op amps from saturating and avoids amplifier slew-rate limitations. Transistor Q1 forms the limit circuit. The design equation for the voltage-limit circuit is:
