Electronic Design UPDATE: January 26, 2005

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Electronic Design UPDATE e-Newsletter
Electronic Design Magazine
PlanetEE ==> www.planetee.com
January 26, 2005
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http://lists.planetee.com/cgi-bin3/DM/y/ei2f0Gl4E70EmQ0BOMK0At

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Today's Table Of Contents:
1. Industry View
  * Look Beyond Peak Data Rate When Judging Memories
2. Focus On ASICs
  * Reference Methodology Eases SoC Integration Of ARC 600 Processor
    Core
3. News From The Editors
  * Filters Battle EMI In Portables With High-Speed I/O
  * RFID Market Set To Come Alive In 2005
  * Optical Cable Assemblies Serve Military Needs
4. Upcoming Industry Events
  * Electronics Circuit World Convention 10
  * Embedded World Exhibition & Conference
  * Second EclipseCon
5. Magazine Highlights: January 13, 2005, Annual Technology Forecast
    Issue
  * Visionaries: Forward-looking technology leaders offer their views of 
    the future of the electronics industry
  * The 2005 Technology Forecast: Electronic Design's own editors 
    deliver what they foresee as the important developments of the coming year

Electronic Design UPDATE edited by Lisa Maliniak, eMedia Editor

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Free Webcast: Next-Generation In-House PCB Prototyping
February 3 at 12:00 p.m. EST

Designers must consider production time, quality, and costs when 
producing prototype circuit boards. In this world of blazing 
time-to-market requirements and fierce R&D expectations, effective 
prototyping is critical to success. As a result, engineers are adopting 
in-house prototyping because of its enhanced technological capabilities 
and clear advantages over outsourcing. Sponsored by LPKF Laser & 
Electronics, this one-hour webcast hosted by Embedded Systems Editor 
Bill Wong will show how you can produce your own printed-circuit-board 
prototypes in-house without the use of hazardous processing chemicals.

To register, go to:
http://lists.planetee.com/cgi-bin3/DM/y/ei2f0Gl4E70EmQ0BOML0Au

*****

Free Webcast Panel: Selecting the Best ASIC Solution, II
January 27 at 2:00 EST

An important consideration when starting an ASIC design is which 
platform to use. Options include a full-cell-based design, a structured 
or platform ASIC, or a field-programmable gate array. If you know the 
performance requirements and your needs for specialized intellectual 
property, you're halfway there. This panel, moderated by Digital ICs/DSP 
Editor Dave Bursky, will examine selection issues and design/performance 
tradeoffs. Panelists from Fujitsu, NEC, and Toshiba will provide their 
views and answer questions regarding the various design approaches.

To register, go to:
http://lists.planetee.com/cgi-bin3/DM/y/ei2f0Gl4E70EmQ0BOMM0Av

*****

THOUGHT YOU'D MISSED THEM? DON'T WORRY, THEY'RE ARCHIVED
Electronic Design's webcasts are available online:

Next-Generation Physical Verification -- Beyond DRC to Yield Enablement: 
Synopsys' techcast explores today's physical verification tools.
http://lists.planetee.com/cgi-bin3/DM/y/ei2f0Gl4E70EmQ0BOMM0Av

Signal Integrity Testing: Michael Lauterbach of LeCroy Corp. describes 
advances in testing for signal integrity.
http://lists.planetee.com/cgi-bin3/DM/y/ei2f0Gl4E70EmQ0BOMM0Av

Selecting the Best ASIC Solution, I: Dave Bursky discusses the selection 
process with a panel of ASIC manufacturers.
http://lists.planetee.com/cgi-bin3/DM/y/ei2f0Gl4E70EmQ0BKve0Aw

*****

BE SURE TO VISIT Electronic Design's Web site, where the power of 
Electronic Design is a mouse click away! Read our Web exclusives, enjoy 
our Quick Poll, discover Featured Vendors, access our archives, share 
viewpoints in our Forums, explore our e-newsletters, and more.

TAKE OUR CURRENT QUICK POLL:

Do you agree with Editor-in-Chief Mark David that the U.S. should lead a 
global effort for a tsunami warning system? 
-- Yes
-- Yes, but only if the rest of the world helps pick up the tab
-- Lend the expertise, but let the Indian Ocean coastal countries pay 
-- No, it's not the U.S.'s responsibility

Go to Electronic Design ==>
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Staff News
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***Electronic Design Adds eMedia Editor
Electronic Design is pleased to announce the addition of Lisa Maliniak 
as eMedia Editor. Lisa is an electrical engineer and experienced 
Technology Editor. She has both a solid understanding of electronics 
technology and extensive knowledge of the information needs of 
Electronic Design's readers. Lisa will work to broaden the editorial 
scope of Electronic Design's eMedia offerings, providing deeper content 
and building greater EE community while facilitating quicker response to 
readers and their online needs. You can contact her at 
mailto:[email protected].

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1. Industry View -- Exclusive to Electronic Design UPDATE
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Look Beyond Peak Data Rate When Judging Memories

By Laura Stark, Vice President, Memory Interface Division, Rambus Inc.

Since the mid-90s, memory technologies have been named according to how 
fast they run, with most branding themselves with a peak data rate. Data 
rate continues to be the most important factor when calculating the 
performance of a memory system. However, no memory device operating in a 
real system can operate at its peak data rate 100% of the time. 
   Designers must take a deeper look into today's published memory 
specifications to determine how well a memory technology will perform 
under real-world conditions. In some systems, two devices with the 
same peak data rate may deliver very different sustained data rates. 
In other systems, a memory technology with a low peak data rate that 
operates efficiently might perform as well as a memory technology 
with a higher peak data rate. 
   As with CPUs, the underlying architecture can impact the efficiency 
of memory technologies, delivering different usable bandwidths in 
different systems. Some of the more important features include bus 
turnarounds, row cycle time (tRC), and column access granularity. 
   Bus turnarounds always result in a certain amount of inactivity on 
the data bus as circuitry inside the memory transitions between 
writing and reading. Different technologies incur different latencies 
when turning around the bus. A 1600-MHz GDDR3 device needs 21 cycles 
of dead time to turn the bus around twice. By comparison, XDR at 3200 
MHz requires six cycles of idle time using a built-in feature called 
"Early Read After Write." Turnaround latencies cause tremendous 
headaches for people who design memory systems that don't have the 
benefit of long, uninterrupted bursts of writes and reads. 
   Bank conflicts cause problems for many systems designers and are 
created primarily due to an interaction between the tRC of a DRAM and 
its bank count. Data in DRAMs is organized in rows and columns with 
data bits stored at their intersections. Each bank is independently 
addressable and does not interfere with the accesses to other banks. 
When a row is opened, it must remain open for a period of at least 
tRC. If a memory controller needs data from a different row within a 
bank, it must wait until tRC is satisfied before attempting to access 
the other data. Each additional bank decreases the probability that 
requested data will exist in a recently accessed bank. So, a shorter 
tRC and more banks ensure more efficient memory access. 
   Column access granularity is the amount of data accessed on each 
memory transaction. Many technologies increase their peak bandwidth 
by increasing the "core prefetch," allowing the DRAM core to operate 
at a lower speed than the I/O. This, however, increases the minimum 
burst length of a memory technology. Increasing the bus width is 
another way to squeeze more total bandwidth from a slower memory 
technology. Widening a 128-bit, 400-MHz interface similar to those 
used in today's PCs to 256 bits would increase memory bandwidth from 
6.4 Gbytes/s to 12.8 Gbytes/s. However, a burst length of four 
(typical in today's memory systems) would produce 128 bytes of data 
per transaction. Many processors operate on smaller amounts of data, 
typically 64 bytes or less. In this case, the high memory system 
bandwidth produces extra data that is wasted by the processor. 
Memories that support narrower bus widths can use core prefetch more 
effectively, matching the requested data size, and increasing memory 
efficiency.
   Additionally, different applications will exhibit varying degrees of 
sensitivity to a memory technology's features. For instance, graphics 
applications typically render images in units of triangles. As 
triangle sizes decrease with new generations of processors, access 
granularity greatly impacts the memory bus efficiency. Servers, on 
the other hand, execute threads that access larger blocks of memory, 
reducing the effect of access granularity. With the advent of 
multithreaded architectures and multicore processors, servers can 
execute many independent blocks of code simultaneously. Each thread 
has its own memory needs and may issue transactions that create bank 
conflicts with other threads. The more threads you have, the more 
bank conflicts you'll see in your memory system. 
   Designers that specify memory technologies for new products should 
take into account the types of access patterns they expect to see in 
their memory systems. For designs that require bursts of writes and 
reads from random locations in memory, a technology optimized for 
reduced bank conflicts and fast turnarounds like XDR will fare well. 
Products that can guarantee long bursts of transactions to contiguous 
addresses in memory will have a lower sensitivity to 
efficiency-reducing phenomena and are good candidates for memory 
technologies like DDR or GDDR. In either case, memory technologies 
that have high peak bandwidth specs should be scrutinized to make 
sure that they will perform adequately in the target application.

Laura Stark co-leads the development and deployment of memory interface 
products, including Rambus RDRAM and XDR DRAM. She joined Rambus in 1996 
and assumed her current job in October 2000. Stark holds a bachelor's 
degree in electrical engineering from the Massachusetts Institute of 
Technology. She can be reached at mailto:[email protected]. 

To comment on this Editor's View, go to Reader Comments at the foot of 
the Web page:

Electronic Design UPDATE ==>
http://lists.planetee.com/cgi-bin3/DM/y/ei2f0Gl4E70EmQ0BOMN0Aw

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2. Focus On ASICs
**********************

***Reference Methodology Eases SoC Integration Of ARC 600 Processor Core
ARC International and Magma Design Automation Inc. have jointly 
developed a validated reference methodology for the ARC 600 configurable 
microprocessor core. The reference methodology, which is available from 
Magma, has been implemented in a 0.13-micron design flow. Based on 
Magma's Blast Create RTL-to-placed gates, Blast Plan Pro hierarchical 
design, and the Blast Fusion physical design tools, the ARC 600 
reference methodology includes flow documentation, floorplanning 
information, tool scripts, and "make" files. In addition, ARC 
International has completed the Magma IP verification process for the 
ARC 600 and has been added to the list of "Magma-Ready" IP providers. 
Customers can take their ARC 600 core-based designs in a single-pass 
flow from RTL directly to placement and routing without leaving the 
Magma system. Users of the ARC 600 core can license the reference 
methodology and the relevant synthesis scripts and sample floorplanning 
information from Magma. The ARC 600 is a configurable and extendible 
32-bit processor core with DSP extensions that also incorporates a 
variety of low-power features, making it an attractive solution for 
portable consumer devices. 
     Magma Design Automation Inc. ==>  http://lists.planetee.com/cgi-bin3/DM/y/ei2f0Gl4E70EmQ0BCfz0At
     ARC International ==> http://lists.planetee.com/cgi-bin3/DM/y/ei2f0Gl4E70EmQ0BEEt0AI

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3. News -- From The Editors
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***Filters Battle EMI In Portables With High-Speed I/O
Three new electromagnetic interference (EMI) filter arrays with 
electrostatic discharge (ESD) protection in thin DFN (TDFN) packages are 
intended for high-speed LCD display and camera data interfaces with 
maximum data rates up to 54 Mbits/s per line. Signal components from 800 
MHz to 2.9 GHz are attenuated by at least 25 dB. The typical 3-dB point 
is 110 MHz. All exhibit extremely low parasitic inductance (10 to 20 pH) 
due to their TDFN-package ground pads. ON Semiconductor's four-channel 
NUF4402 is priced at $0.25 per unit in 10,000-unit quantities. The 
six-channel NUF6401 is $0.33 per unit, and the eight-channel NUF8401 is 
$0.44 per unit. They're available in production quantities now.
     ON Semiconductor ==> http://lists.planetee.com/cgi-bin3/DM/y/ei2f0Gl4E70EmQ08e60AT


***RFID Market Set To Come Alive In 2005
A recent report from Deloitte & Touche's Media and Telecommunications 
industry group predicts that the mobile and wireless market will 
maintain positive growth throughout 2005, fueled in large part by the 
transition of radio-frequency identification (RFID) technology from the 
labs into the commercial world. The combined influence of major retail 
chains, defense contractors, automotive manufacturers, and others -- all 
of whom are requiring suppliers to use RFID -- will prompt a massive 
increase in RFID adoption. According to Deloitte's report, current RFID 
adoption is essentially zero, but by year's end more than 10 billion 
RFID tags will have been sold and used. Overall telecommunications 
growth will also be stimulated by cellular phone expansion into 
developing countries and increased usage of Voice over Internet Protocol 
and broadband services.
     Deloitte & Touche LLP ==> http://lists.planetee.com/cgi-bin3/DM/y/ei2f0Gl4E70EmQ0BOMP0Ay

***Optical Cable Assemblies Serve Military Needs
Molex Inc. has introduced a new line of optical military cable 
assemblies for a variety of military, avionics, flight control, 
EMI-sensitive, and security applications. These high-end military-style 
connector products are available with fiber-optic MIL-T-19504 approved 
terminals, commercial-off-the-shelf (COTS) cabling, and fiberoptic 
connectors. The cable assemblies use ruggedized connectors designed for 
harsh environments. They can be terminated to both single-fiber and 
ribbon cable, and they're available in two- to 29-pin configurations to 
meet MIL-STD-1560 requirements. Various finish types are also offered 
with plug, jam-nut, and wall-mount receptacle options. Cable assembly 
pricing varies by construction type and length, and it starts around 
$400. Short lead times, typically between six to 10 weeks, are 
available.
     Molex Inc. ==> 
http://lists.planetee.com/cgi-bin3/DM/y/ei2f0Gl4E70EmQ0BOMQ0Az

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4. Upcoming Industry Events
**********************

Feb. 21-24, Electronics Circuit World Convention 10 (IPC Printed 
Circuits EXPO, APEX, Designers Summit)
Anaheim, Calif.
http://lists.planetee.com/cgi-bin3/DM/y/ei2f0Gl4E70EmQ0BN170A5 

Feb. 22-24, Embedded World Exhibition & Conference
Nuremberg, Germany
http://lists.planetee.com/cgi-bin3/DM/y/ei2f0Gl4E70EmQ0BOMS0A2 

Feb. 28-March 3, Second EclipseCon
Burlingame, Calif.
http://lists.planetee.com/cgi-bin3/DM/y/ei2f0Gl4E70EmQ0BOMT0A3 

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5. Magazine Highlights
**********************
In case you missed them, here are some of the high points of our most 
recent issue.

January 13, 2005, Annual Technology Forecast Issue:

* Visionaries
Forward-looking technology leaders offer their views of the future of 
the electronics industry.
http://lists.planetee.com/cgi-bin3/DM/y/ei2f0Gl4E70EmQ0BOMU0A4

* The 2005 Technology Forecast
Electronic Design's own editors deliver what they foresee as the 
important developments of the coming year in:
  Digital ICs
  Analog/Mixed-Signal
  Components
  Power
  Communications
  EDA
  Embedded
  Test & Measurement
http://lists.planetee.com/cgi-bin3/DM/y/ei2f0Gl4E70EmQ0BOMU0A4

For the complete Table of Contents, go to Electronic Design ==>
http://lists.planetee.com/cgi-bin3/DM/y/ei2f0Gl4E70EmQ0BOMU0A4

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CONTACTS: Electronic Design UPDATE e-NEWSLETTER
==================================

Editorial: Mark David, Editor-in-Chief
mailto:[email protected]

Advertising/Sponsorship Opportunities: Bill Baumann, Publisher:
mailto:[email protected]
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