Orders were up for Emerson Process Management’s largest-selling product when a supplier of a critical ASIC component unexpectedly issued an end-of-life notice for its part.
A major supplier of automation systems and instrumentation, Emerson had to come up with a new mixed-signal ASIC for its Rosemount 3051CDæan industrial differential pressure transmitteræand they needed to do it fast. The ASIC, known as the Marble sensor interface chip, accepts input from a capacitive pressure sensor and converts it to digital data for further processing.
With AMI Semiconductor (AMIS) as its development partner, Emerson finished the development project in less than 50 weeks, or about half the time generally required to execute such a project. But Terry Krouth, Emerson’s VP of technology, said it was no easy task.
"There was really no good alternative (to the Marble sensor chip)," said Krouth. "It offered low power, small size, reliability, and a good cost position. We couldn’t design it out."
Krouth said a second spin of silicon is needed for roughly half of Emerson’s IC projects. But with supplies of the marble chip dwindling, there wasn’t enough time. "Getting it right the first time was imperative."
Emerson selected AMIS as its ASIC development partner because it had worked successfully with AMIS on other ASICs, and because AMIS was willing to adapt its design flow to fit Emerson’s tight timeframe.
AMIS’ design flow begins with a detailed planning stage during which design and test specifications, statements of work and other technical definitions and resource plans are developed. AMIS spends more time in pre-study than is typical with most design flows, according to Krouth.
"Experience has shown that if more time is spent up-front, asking critical questions, there is a much higher probability of first time silicon success," he said. "Designers can focus on implementation of a detailed plan.
Krouth said as many as ten people from each company worked on the project in program management, design, layout, testing, and product engineering. Approximately 60% of the project involved analog design. Digital design accounted for 20%, test development 15%, and feasibility and requirements 5%.
The team first had to design the ASIC, and then ensure that it worked in the transmitter. The original specification was reviewed and rewritten to capture detailed requirements that were subsequently translated to converter specifications.
"This is sometimes a difficult process that can take a few months, but for this project it was limited to a few weeks," Krouth said. "The detailed requirements had to be agreed to quickly upfront in order to have any hope of meeting our schedule."
The new chip had to be pin-for pin-compatible with the old design with no layout modifications to the 3051CD circuit boards except for a value change to the bias resistor that supplies current to the converter circuit.
Although it is functionally identical to its predecessor, the new chip uses a two-phase converter architecture instead of the four-phase design in the earlier chip. It’s designed with switched capacitor (versus resistive) feedback, and also includes a new anti-foldback circuit and new test pin functionality. Digital circuitry in the new converter provides a different clocking architecture.
"The most difficult performance goal was to meet two different product specifications within the required operating currents, which are as low as 175µA in one of the product applications, and still maintain the required converter specifications," Krouth said.
Ryan Cameron, AMIS’ North America product line manager for mixed signal ASICs, added that proprietary methods involving both design and layout were used to account for ESD events, overcurrent and overvoltage situations, and latch-up concerns arising from the environmentally harsh, electrically noisy environments in which Rosemount 3051CD operates.
Cameron said AMIS ran extensive simulations on the main functional blocks and sub-circuits of the design. "Special attention was also given to symmetry in layout, noise barrier and guard ring design, and digital and analog floor planning to limit cross-talk," he noted. "Many iterations were performed between the analog and layout engineers to refine the design and layout architecture. The initial release of the chip had to work the first time so there was no room for any errors."
Emerson’s Krouth said that during design, extensive mixed-signal simulation and back-annotated simulation techniques were implemented to avoid common analog/digital interface issues. "Some design houses do not do post-layout simulations to prove that there are no layout issues," he noted. "If these extra steps are not taken, they usually result in costly second, or even third iterations of the chip to get it right."
"What made this project unusual was the degree to which Emerson was willing to share information about its application; also the fact that both firms used the same development tools," said Bob Klosterboer, AMIS’ senior vice president for integrated mixed-signal products. The tools included Cadence’s Assura for physical verification.
"Having the same development tools was critical," Klosterboer continued. "Since Emerson was doing the design and analog portion of the layout, file transfers and exchange of design information was critical. In the past, trying to translate design information from one tools format to another has always been difficult, and can cause delays in the schedule."
Krouth said the project represented "the fastest turn ever" from definition to an approved quality part. "With support from AMIS on design and layout, we were able to hand off a design that they could put into production almost immediately. There was a very short timeæfourteen and-a-half weeksæbetween hand-off and tape-out."
AMIS’ Cameron said time was saved on the project because Emerson had existing parts to give to AMIS’ test engineers. "Typically, test development needs silicon, but in this case we were able to use the existing parts to develop the test in parallel with design and fabrication."
Emerson also provided a product test board to aid testing and verification. "If a customer isn’t willing to give us insight into the end application, it’s difficult to correlate our results with theirs," Cameron noted. "If we don’t have an identical application board for evaluating the part, we see one thing and the customer sees another."
Cameron said Emerson laid out the analog core and designed the digital portion in VHDL, and then transmitted the design files to AMIS for digital layout and final integration. AMIS designed a custom peripheral pad ring for Emerson’s analog core and routed the top level of the circuit, placing the analog core inside the pad ring, routing the digital core, wrapping the cores with the pad ring, and performing top-level verification. The pad ring was designed to incorporate AMIS’ ESD structures, with special attention paid to critical sensor inputs and isolation barriers.
In the end, AMIS fabricated the part on a 0.5_-process significantly tighter than that used by the previous manufacturer Cameron said the replacement ASIC sped through AMIS’ manufacturing facility in 15 days, from ordering masks to prototype delivery and acceptance. That cycle typically takes six to eight weeks. The project was given top priority at each step, with other lots temporarily set aside.
"We cut the fab time by as much as 60%," Cameron said. Chips were then routed to AMIS’ quick-turn assembly facility, diced, and assembled into ceramic packages. "We took them to the test floor, brought the test up, tested 50 prototypes and hand-carried them to Emerson. Within about half an hour, we got the thumbs-up."