PLL Accepts Multiple Frequency Inputs

    Feb. 1, 2000
    The MK2049-02 phase-locked loop (PLL) generates T1, E1, T3, E3 and other communication frequencies using an 8-kHz clock input as a reference. The device also accepts T1, E1, T3, and E3 input clocks and provides the same output for loop timing. It

    The MK2049-02 phase-locked loop (PLL) generates T1, E1, T3, E3 and other communication frequencies using an 8-kHz clock input as a reference. The device also accepts T1, E1, T3, and E3 input clocks and provides the same output for loop timing. It also has a jitter attenuated buffer capability. All outputs are frequency locked both together and to the input. Other features include a 20-pin SOIC package, fixed input-output phase relationship, and 5V ±10% operation.

    Company: ELECTRONICS 2000 LTD.

    Product URL: Click here for more information

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