PLL Cleans, Multiplies And Divides Input Frequencies

The Model M2016 phase locked loop (PLL) comes in a seven-pin, thru-hole package that houses a phase/frequency error detector, error signal filter, and voltage-controlled crystal oscillator (VCXO), which represent all of the key components of a crystal-stabilized PLL. The device is used to clean up noisy wireless transmission, extract clock signals from data waveforms, and synthesize radio receiver IF frequencies. The PLL can stretch or shrink timing waveforms, develop time bases, and multiply or divide reference frequencies by precision ratios. It is a fully functioning PLL subsystem for multiplying, dividing and cleaning input frequencies. Housed in a hermetically-sealed 7-pin DIL package, the PLL operates from a 4.5 to 5.5 Vdc supply, draws 50 mA maximum current, and develops output frequencies between 10 and 32.768 MHz. It will process input signals in the range 5 kHz to 10 MHz and frequency capture range is 150 ppm. Typical output symmetry is 45/55, jitter is as low as 5 psRMS, depending on incoming signal characteristics.