32-Bit Quadrature Counter’s Serial Interface Reduces IO Wire Count

The LS7366R IC performs decoding and counting of quadrature clocks directly from incremental encoders. It’s a dedicated solution to position and displacement tracking at 40 x 106/sec. line rate (at 5 V) from the encoder and a count limit of 232. A serial interface (SPI) greatly reduces the required IO wire count as compared to a parallel bus structure. The counter can also operate with non-quadrature clock signals and provides various counting modes for signal conditioning. Operating voltage range is 3 V to 5.5 V. Programming of the LS7366R and all communications between itself and a host controller is done with four simple instructions: READ_reg, WRITE_reg, LOAD_reg, and CLEAR_reg. The functional modes are controlled with two bytes of data written into two on-chip mode registers. The count-related status is stored in a status register. A 32-bit input register and a 32-bit comparator is provided for comparing a target value with the instantaneous count. Two maskable output flags are also provided for signaling count related events, and the index and the quadrature inputs are digitally filtered for noise suppression. The LS7366R is offered in 14-Pin DIP, SOIC, and TSSOP packages. Pricing in 1000-piece quantities is $1.60. LSI COMPUTER SYSTEMS INC., Melville, NY. (631) 271-0400.