Build a simple finite state machine
Probably everyone has seen in some textbook the block diagram of a “finite state machine” (FSM), and most likely nobody used it in practice (Fig. 1). For the few who aren’t familiar with it, an FSM is a device that can assume a finite number of states. Each of them contains a complete description of a particular condition of the FSM. The FSM can only jump from state to state, depending on the state where the machine is, as well as the input.
A simple FSM is made using an EPROM, in which data is fed back to its addresses. The data indicates the state of the machine. The next state is the content of the EPROM cell, which is addressed by the present state (lowest part of the address) and the input lines (highest part of the address). An FSM that uses an 8-bit memory chip has 256 states and can perform simple operations. The difficulty in designing such a device involves generating binary code for the EPROM. To accomplish this task, a simple language was defined that, in its simplest form, has instructions like the following:
where indicates the actual state of the machine and may be followed by the binary string if it’s required that the state have a defined bit configuration; and where , after the reserved word “if” gives the condition to bring the system to , which may be followed (like ) by . The optional reserved word “else” will allow the system to jump to an . The compiler (written in Borland Turbo Pascal 5.5) reads the test file, and produces a binary file used to program the EPROM. To illustrate how to design a simple device using the “finite state language,” a simple four-phase stepper-motor control was implemented (Listing 1). The compiler associates a progressive number with each label and each EPROM output, taking care of the (binary numbers in parentheses) (Listing 2). Then the compiler computes the EPROM content (Listing 3). The compiler assumes that the default state is the first state of the source code. Thus, any unspecified condition jumps to that state (state stop).
Figure 2 depicts the schematic that implements the hardware for this FSM.
